Lines Matching +full:bit0 +full:- +full:7
2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
105 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
106 #define ATOM_INIT (ATOM_DISABLE+7)
127 #define ATOM_TV_PAL60 7
146 /* Bit0:{=0:single, =1:dual},
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
358 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
362 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
397 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
398 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
402 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
403 …ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYT…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
677 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
680 // 7: ATOM_ENCODER_INIT Initialize DAC
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
868 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
966 // =0: lane 0~3 or 0~7
967 // =1: lane 4~7
1013 #define ATOM_TRANSMITTER_ACTION_INIT 7
1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1051 //Bit0
1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1130 //Bit0
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1229 //Bit0
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1573 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1626 …// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the sour…
1654 // =1: other external clock source, which is pre-defined
1656 // bit[7:5]: reserved.
1702 …// =1: other external clock source, which is pre-defined …
1704 // bit[7:5]: reserved.
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1830 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1939 // Bit[1]: 1-Ext. 0-Int.
1941 // Bits[7:4] reserved
1943 …USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11…
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1964 // Bit[1]: 1-Ext. 0-Int.
1966 // Bits[7:4] reserved
1968 …USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11…
2018 UCHAR ucMisc; // bit0=0: Enable single link
2042 UCHAR ucTruncate; // bit0=0: Disable truncate
2046 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2050 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2089 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2149 // bit1=0: non-coherent mode
2380 …SIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2404 …o; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2416 … ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2417 … ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2419 …er voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2420 … input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2421 …AR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2422 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2423 …eoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2424 …eoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2425 …eoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2426 …eoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2427 …eoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2762 …USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI suppor…
2765 …USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2…
2771 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is re…
2781 … For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2799 … duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it…
2833 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2857 … // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2867 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2868 … or user customized mode. In this case, driver will just stick to this boot-up mode. No other Pow…
2879 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using l…
2886 …ord is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEV…
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2889 …[7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are suppor…
2892 …[3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lan…
2893 …7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station …
2896 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2898 [15:8] - Lane configuration attribute;
2899 [23:16]- Connector type, possible value:
2905 [31:24]- Reserved
2913 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offs…
2917 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits rese…
2927 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
2955 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition
3016 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3153 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported
3154 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported
3155 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported
3156 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported
3157 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported
3158 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported
3159 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported
3160 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3162 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported
3163 // Bit 10 = 0 - no DFP4 support= 1- DFP4 is supported
3164 // Bit 11 = 0 - no DFP5 support= 1- DFP5 is supported
3172 // [7:0] - I2C LINE Associate ID
3173 // = 0 - no I2C
3174 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection)
3176 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use
3178 // = 3-7 Reserved for future I2C engines
3179 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3284 // usModeMiscInfo-
3296 //usRefreshRate-
3427 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3447 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3478 // 0 0 0 - Color bit depth is undefined
3479 // 0 0 1 - 6 Bits per Primary Color
3480 // 0 1 0 - 8 Bits per Primary Color
3481 // 0 1 1 - 10 Bits per Primary Color
3482 // 1 0 0 - 12 Bits per Primary Color
3483 // 1 0 1 - 14 Bits per Primary Color
3484 // 1 1 0 - 16 Bits per Primary Color
3485 // 1 1 1 - Reserved
3509 // Bit0: {=0:single, =1:dual},
3520 … // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3523 // Bit7-3: Reserved
3561 // 0 0 0 - Color bit depth is undefined
3562 // 0 0 1 - 6 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3564 // 0 1 1 - 10 Bits per Primary Color
3565 // 1 0 0 - 12 Bits per Primary Color
3566 // 1 0 1 - 14 Bits per Primary Color
3567 // 1 1 0 - 16 Bits per Primary Color
3568 // 1 1 1 - Reserved
3585 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip
3586 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip with…
3685 //ATOM_TV_PAL60 7
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3729 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
3741 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3754 …(ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3812 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)…
3835 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3839 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3841 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3885 //ucGPIO_ID pre-define id for multiple usage
3909 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7]
3922 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7];
3943 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7
3958 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3967 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3984 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4077 #define EXT_HPDPIN_LUTINDEX_7 7
4087 #define EXT_AUXDDC_LUTINDEX_7 7
4095 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: fro…
4115 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: …
4150 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7
4160 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4183 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7
4288 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4319 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4341 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4343 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4345 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability.
4347 …USHORT usReserved:14; // Bit1-15 may be defined for other capability in fu…
4479 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4480 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4573 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_V…
4574 …I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OB…
4575 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GP…
4576 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SV…
4578 …OST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4579 …AKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4580 …AKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE…
4635 // 14:7 – PSI0_VID
4864 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
4889 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
4890 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
4892 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
4895 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
4898 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
4909 Bit[1]=0: DDR-DLL shut-down feature disabled.
4910 1: DDR-DLL shut-down feature enabled.
4911 Bit[2]=0: DDR-PLL Power down feature disabled.
4912 … 1: DDR-PLL Power down feature enabled.
4924 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
4931 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
4944 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5079 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5113 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5114 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5116 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5119 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5122 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5133 Bit[1]=0: DDR-DLL shut-down feature disabled.
5134 1: DDR-DLL shut-down feature enabled.
5135 Bit[2]=0: DDR-PLL Power down feature disabled.
5136 … 1: DDR-PLL Power down feature enabled.
5150 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5157 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconne…
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5170 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5179 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5182 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5186 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5190 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5280 … Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine…
5314 …When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways …
5315 …1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determin…
5317 … Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5320 …2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only ind…
5323 …Changing BL using VBIOS function could be functional in both driver and non-driver present environ…
5333 Bit[1]=0: DDR-DLL shut-down feature disabled.
5334 1: DDR-DLL shut-down feature enabled.
5335 Bit[2]=0: DDR-PLL Power down feature disabled.
5336 1: DDR-PLL Power down feature enabled.
5349 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
5357 … NCLK speed while memory runs in self-refresh state, used to calculate self-re…
5375 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1:…
5385 …default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5389 …fault which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5393 …t delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5397 …fault which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5417 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State
5418 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5419 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded
5488 #define ASIC_INTERNAL_SS_ON_DP 7
5502 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS …
5533 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS …
5557 #define ATOM_DOS_MODE_INFO_DEF 7
5888 #define ATOM_S6_DOCK_STATE_SHIFT 7
5981 …char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<cha…
5983 …ADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevisio…
5984 …DER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevisi…
5988 …SION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevisio…
5989 …ION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevisi…
6369 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode
6398 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6400 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6406 … ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, …
6407 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6408 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6425 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6427 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6433 … ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, …
6434 …fault MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6435 …fault MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6469 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6496 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6529 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6557 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6567 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6582 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6603 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6605 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6608 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6611 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6613 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6645 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6647 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6650 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6653 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6655 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6664 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6676 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6678 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6681 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6684 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6686 … // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6695 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6714 … // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
6715 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6716 …Size; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
6722 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6725 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6758 …ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) …
6840 #define VESA_MODE_WIN_ATTRIBUTE 7
6928 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
6941 ULONG Reserved_1; // dd 0 ; reserved - always set to 0
6942 USHORT Reserved_2; // dw 0 ; reserved - always set to 0
6985 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7
7293 #define SELECT_CRTC_PIXEL_RATE 7
7299 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7300 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7301 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7308 …et; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Lin…
7309 …USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mo…
7310 …USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mo…
7432 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7437 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7442 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7450 // [7:4] - connector type
7451 // = 1 - VGA connector
7452 // = 2 - DVI-I
7453 // = 3 - DVI-D
7454 // = 4 - DVI-A
7455 // = 5 - SVIDEO
7456 // = 6 - COMPOSITE
7457 // = 7 - LVDS
7458 // = 8 - DIGITAL LINK
7459 // = 9 - SCART
7460 // = 0xA - HDMI_type A
7461 // = 0xB - HDMI_type B
7462 // = 0xE - Special case1 (DVI+DIN)
7464 // [3:0] - DAC Associated
7465 // = 0 - no DAC
7466 // = 1 - DACA
7467 // = 2 - DACB
7468 // = 3 - External DAC
7533 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7599 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
7643 …SCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-…
7653 …ETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-Hi…
7663 …O2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver …