Lines Matching +full:8 +full:khz
79 #define ATOM_EXT_PLL1 8
107 #define ATOM_GET_STATUS (ATOM_DISABLE+8)
128 #define ATOM_TV_SECAM 8
358 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
359 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
361 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
362 …USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword…
444 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
445 ULONG ulClockFreq:24; // in unit of 10kHz
447 ULONG ulClockFreq:24; // in unit of 10kHz
448 …ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PL…
476 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
483 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
487 …ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register d…
584 ULONG ulTargetEngineClock; //In 10Khz unit
589 ULONG ulTargetEngineClock; //In 10Khz unit
598 ULONG ulTargetMemoryClock; //In 10Khz unit
603 ULONG ulTargetMemoryClock; //In 10Khz unit
612 ULONG ulDefaultEngineClock; //In 10Khz unit
613 ULONG ulDefaultMemoryClock; //In 10Khz unit
676 USHORT usPixelClock; // in 10KHz; for bios convenient
692 USHORT usPixelClock; // in 10KHz; for bios convenient
769 USHORT usPixelClock; // in 10KHz; for bios convenient
844 USHORT usPixelClock; // in 10KHz; for bios convenient
900 USHORT usPixelClock; // in 10KHz; for bios convenient
952 USHORT usPixelClock; // in 10KHz; for bios convenient
953 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
958 // =1: 8 lane Link ( Dual Links TMDS )
968 // =2: lane 8~11 or 8~15
1014 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
1080 USHORT usPixelClock; // in 10KHz; for bios convenient
1081 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1119 USHORT usPixelClock; // in 10KHz; for bios convenient
1120 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1214 USHORT usPixelClock; // in 10KHz; for bios convenient
1215 …USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid…
1273 …USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= p…
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1364 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1544 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1564 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1611 …USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_D…
1672 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1679 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
1813 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
1822 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
1829 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1943 … usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1957 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
1968 … usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1983 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
2002 ULONG ulTargetMemoryClock; //In 10Khz unit
2017 USHORT usPixelClock; // in 10KHz; for bios convenient
2038 USHORT usPixelClock; // in 10KHz; for bios convenient
2248 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7…
2330 USHORT usPixelClock; // in 10KHz; for bios convenient
2510 ULONG ulDefaultEngineClock; //In 10Khz unit
2511 ULONG ulDefaultMemoryClock; //In 10Khz unit
2512 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2513 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2514 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2515 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2516 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2517 ULONG ulASICMaxEngineClock; //In 10Khz unit
2518 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2522 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2523 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2524 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2525 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2526 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2527 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2528 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2529 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2530 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2531 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above…
2533 USHORT usReferenceClock; //In 10Khz unit
2544 ULONG ulDefaultEngineClock; //In 10Khz unit
2545 ULONG ulDefaultMemoryClock; //In 10Khz unit
2546 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2547 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2548 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2549 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2550 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2551 ULONG ulASICMaxEngineClock; //In 10Khz unit
2552 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2557 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2558 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2559 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2560 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2561 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2562 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2563 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2564 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2565 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2566 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2567 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2569 USHORT usReferenceClock; //In 10Khz unit
2580 ULONG ulDefaultEngineClock; //In 10Khz unit
2581 ULONG ulDefaultMemoryClock; //In 10Khz unit
2582 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2583 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2584 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2585 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2586 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2587 ULONG ulASICMaxEngineClock; //In 10Khz unit
2588 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2593 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2594 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2595 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2596 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2597 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2598 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2599 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2600 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2601 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2602 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2603 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2604 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2606 USHORT usReferenceClock; //In 10Khz unit
2617 ULONG ulDefaultEngineClock; //In 10Khz unit
2618 ULONG ulDefaultMemoryClock; //In 10Khz unit
2619 ULONG ulDriverTargetEngineClock; //In 10Khz unit
2620 ULONG ulDriverTargetMemoryClock; //In 10Khz unit
2621 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2622 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2623 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2624 ULONG ulASICMaxEngineClock; //In 10Khz unit
2625 ULONG ulASICMaxMemoryClock; //In 10Khz unit
2631 ULONG ul3DAccelerationEngineClock;//In 10Khz unit
2632 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2633 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2634 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2635 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2636 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2637 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2638 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2639 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2640 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2641 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2642 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2644 USHORT usReferenceClock; //In 10Khz unit
2656 ULONG ulDefaultEngineClock; //In 10Khz unit
2657 ULONG ulDefaultMemoryClock; //In 10Khz unit
2660 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
2661 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
2662 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2664 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit
2671 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2672 USHORT usMinEngineClockPLL_Input; //In 10Khz unit
2673 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
2674 USHORT usMinEngineClockPLL_Output; //In 10Khz unit
2675 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
2676 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
2677 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
2678 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
2679 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2680 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2681 …USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMin…
2683 USHORT usCoreReferenceClock; //In 10Khz unit
2684 USHORT usMemoryReferenceClock; //In 10Khz unit
2685 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2697 ULONG ulDefaultEngineClock; //In 10Khz unit
2698 ULONG ulDefaultMemoryClock; //In 10Khz unit
2699 ULONG ulSPLL_OutputFreq; //In 10Khz unit
2700 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit
2701 … ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2702 … ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2703 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
2705 …ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency…
2712 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
2717 …USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz uni…
2718 USHORT usMinPixelClockPLL_Input; //In 10Khz unit
2719 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
2722 USHORT usCoreReferenceClock; //In 10Khz unit
2723 USHORT usMemoryReferenceClock; //In 10Khz unit
2724 …USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mod…
2750 ULONG ulBootUpEngineClock; //in 10kHz unit
2751 ULONG ulBootUpMemoryClock; //in 10kHz unit
2752 ULONG ulMaxSystemMemoryClock; //in 10kHz unit
2753 ULONG ulMinSystemMemoryClock; //in 10kHz unit
2765 …USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2…
2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2795 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max …
2796 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min …
2798 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value…
2799 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the valu…
2801 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the ma…
2802 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min…
2822 ULONG ulBootUpEngineClock; //in 10kHz unit
2824 ULONG ulBootUpUMAClock; //in 10kHz unit
2825 ULONG ulBootUpSidePortClock; //in 10kHz unit
2826 ULONG ulMinSidePortClock; //in 10kHz unit
2843 ULONG ulHTLinkFreq; //in 10Khz
2850 ULONG ulHighVoltageHTLinkFreq; // in 10Khz
2851 ULONG ulLowVoltageHTLinkFreq; // in 10Khz
2862 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz;
2863 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2864 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not …
2881 Bit[8]=1: CDLF is supported and enabled on current system.
2888 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2892 …ot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2893 …ctor on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2896 …one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connect…
2898 [15:8] - Lane configuration attribute;
2929 ulHTLinkFreq: Bootup HT link Frequency in 10Khz.
2995 ULONG ulBootUpEngineClock; //in 10kHz unit
2996 …ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the sourc…
2997 …ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relation…
2998 ULONG ulBootUpUMAClock; //in 10kHz unit
2999 ULONG ulReserved1[8]; //must be 0x0 for the reserved
3161 // Bit 8 = 0 - no CV support= 1- CV is supported
3376 USHORT usPixelClock; //in 10Khz unit
3480 // 0 1 0 - 8 Bits per Primary Color
3563 // 0 1 0 - 8 Bits per Primary Color
3686 //ATOM_TV_SECAM 8
3752 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8=…
4144 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4184 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD…
4320 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8
4505 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
4577 #define VOLTAGE_OBJ_EVV 8
4666 …USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse i…
4775 …mSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4780 …upportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz
4864 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
4865 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
4866 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
4906 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
4931 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
4932 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5079 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5080 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5081 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5130 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on W…
5157 … Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5158 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5179 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
5186 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
5209 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB ps…
5280 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equa…
5281 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit.
5282 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit.
5357 …eed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
5385 …=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->…
5393 …=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following:…
5416 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-…
5472 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz
5474 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq
5489 #define ASIC_INTERNAL_SS_ON_DCPLL 8
5497 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5528 … ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5558 #define ATOM_I2C_CHANNEL_STATUS_DEF 8
5663 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8
5765 #define ATOM_S4_LCD1_REFRESH_SHIFT 8
5806 (ATOM_S5_DOS_FORCE_CVb3<<8))
5889 #define ATOM_S6_CRITICAL_STATE_SHIFT 8
5914 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8
5940 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SH…
5941 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHAN…
5942 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTN…
5943 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHAN…
5944 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_…
5946 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_S…
5947 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_S…
5949 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANG…
5950 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_…
5951 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_…
5953 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STA…
5954 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWE…
5955 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_S…
5957 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_ST…
5958 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_ST…
5960 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
5961 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
5963 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
5964 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_…
5966 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_C…
5968 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STA…
5970 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISP…
5971 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_…
5972 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_…
5973 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_…
6004 ULONG ulTargetMemoryClock; //In 10Khz unit
6106 USHORT usMemoryStart; //in 8Kb boundary, offset from memory base address
6107 USHORT usMemorySize; //8Kb blocks aligned
6268 ULONG ucMemBlkId:8;
6272 ULONG ucMemBlkId:8;
6400 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6427 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6443 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6479 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6512 …ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below t…
6563 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6608 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6626 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6650 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6662 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6681 … // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
6693 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6723 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6742 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6784 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
7208 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 )
7294 #define SELECT_VGA_BLK 8
7414 USHORT usMaxFrequency; // in 10kHz unit
7458 // = 8 - DIGITAL LINK
7545 USHORT usMaxFrequency; // in 10Khz
7717 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8
7925 UCHAR OemTableId[8]; //UINT64 OemTableId;