Lines Matching +full:0 +full:x12
29 #define ST7703_CMD_ALL_PIXEL_OFF 0x22
30 #define ST7703_CMD_ALL_PIXEL_ON 0x23
31 #define ST7703_CMD_SETAPID 0xB1
32 #define ST7703_CMD_SETDISP 0xB2
33 #define ST7703_CMD_SETRGBIF 0xB3
34 #define ST7703_CMD_SETCYC 0xB4
35 #define ST7703_CMD_SETBGP 0xB5
36 #define ST7703_CMD_SETVCOM 0xB6
37 #define ST7703_CMD_SETOTP 0xB7
38 #define ST7703_CMD_SETPOWER_EXT 0xB8
39 #define ST7703_CMD_SETEXTC 0xB9
40 #define ST7703_CMD_SETMIPI 0xBA
41 #define ST7703_CMD_SETVDC 0xBC
42 #define ST7703_CMD_UNKNOWN_BF 0xBF
43 #define ST7703_CMD_SETSCR 0xC0
44 #define ST7703_CMD_SETPOWER 0xC1
45 #define ST7703_CMD_SETECO 0xC6
46 #define ST7703_CMD_SETIO 0xC7
47 #define ST7703_CMD_SETCABC 0xC8
48 #define ST7703_CMD_SETPANEL 0xCC
49 #define ST7703_CMD_SETGAMMA 0xE0
50 #define ST7703_CMD_SETEQ 0xE3
51 #define ST7703_CMD_SETGIP1 0xE9
52 #define ST7703_CMD_SETGIP2 0xEA
53 #define ST7703_CMD_UNKNOWN_EF 0xEF
88 0xF1, 0x12, 0x83);
90 0x10, 0x10, 0x05, 0x05, 0x03, 0xFF, 0x00, 0x00,
91 0x00, 0x00);
93 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70,
94 0x00);
95 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E);
96 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B);
97 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
98 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xF0, 0x12, 0x30);
100 0x07, 0x07, 0x0B, 0x0B, 0x03, 0x0B, 0x00, 0x00,
101 0x00, 0x00, 0xFF, 0x00, 0xC0, 0x10);
102 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x08, 0x08);
105 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x3F, 0x3F);
106 mipi_dsi_generic_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
108 0x82, 0x10, 0x06, 0x05, 0x9E, 0x0A, 0xA5, 0x12,
109 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
110 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
111 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
112 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
113 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
114 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
117 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
118 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
119 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
120 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
121 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0A,
124 0xA5, 0x00, 0x00, 0x00, 0x00);
126 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41, 0x37,
127 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10, 0x11,
128 0x18, 0x00, 0x09, 0x0E, 0x29, 0x2D, 0x3C, 0x41,
129 0x37, 0x07, 0x0B, 0x0D, 0x10, 0x11, 0x0F, 0x10,
130 0x11, 0x18);
165 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xF1, 0x12, 0x83);
168 0x33, /* VC_main = 0, Lane_Number = 3 (4 lanes) */
169 0x81, /* DSI_LDO_SEL = 1.7V, RTERM = 90 Ohm */
170 0x05, /* IHSRX = x6 (Low High Speed driving ability) */
171 0xF9, /* TX_CLK_SEL = fDSICLK/16 */
172 0x0E, /* HFP_OSC (min. HFP number in DSI mode) */
173 0x0E, /* HBP_OSC (min. HBP number in DSI mode) */
175 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
176 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02,
177 0x4F, 0x11, 0x00, 0x00, 0x37);
180 0x25, /* PCCS = 2, ECP_DC_DIV = 1/4 HSYNC */
181 0x22, /* DT = 15ms XDK_ECP = x2 */
182 0x20, /* PFM_DC_DIV = /1 */
183 0x03 /* ECP_SYNC_EN = 1, VGX_SYNC_EN = 1 */);
187 0x10, /* VBP_RGB_GEN */
188 0x10, /* VFP_RGB_GEN */
189 0x05, /* DE_BP_RGB_GEN */
190 0x05, /* DE_FP_RGB_GEN */
192 0x03, 0xFF,
193 0x00, 0x00,
194 0x00, 0x00);
198 0x73, /* N_POPON */
199 0x73, /* N_NOPON */
200 0x50, /* I_POPON */
201 0x50, /* I_NOPON */
202 0x00, /* SCR[31,24] */
203 0xC0, /* SCR[23,16] */
204 0x08, /* SCR[15,8] */
205 0x70, /* SCR[7,0] */
206 0x00 /* Undocumented */);
209 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x4E);
212 * SS_PANEL = 1 (reverse scan), GS_PANEL = 0 (normal scan)
215 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0B);
218 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
222 0xF0, /* NL = 240 */
223 0x12, /* RES_V_LSB = 0, BLK_CON = VSSD,
226 0xF0 /* WHITE_GND_EN = 1 (GND),
228 * ISC = 0 frames
232 0x00, /* PNOEQ */
233 0x00, /* NNOEQ */
234 0x0B, /* PEQGND */
235 0x0B, /* NEQGND */
236 0x10, /* PEQVCI */
237 0x10, /* NEQVCI */
238 0x00, /* PEQVCI1 */
239 0x00, /* NEQVCI1 */
240 0x00, /* reserved */
241 0x00, /* reserved */
242 0xFF, /* reserved */
243 0x00, /* reserved */
244 0xC0, /* ESD_DET_DATA_WHITE = 1, ESD_WHITE_EN = 1 */
245 0x10 /* SLPIN_OPTION = 1 (no need vsync after sleep-in)
246 * VEDIO_NO_CHECK_EN = 0
247 * ESD_WHITE_GND_EN = 0
248 * ESD_DET_TIME_SEL = 0 frames
251 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x01, 0x00, 0xFF, 0xFF, 0x00);
254 0x74, /* VBTHS, VBTLS: VGH = 17V, VBL = -11V */
255 0x00, /* FBOFF_VGH = 0, FBOFF_VGL = 0 */
256 0x32, /* VRP */
257 0x32, /* VRN */
258 0x77, /* reserved */
259 0xF1, /* APS = 1 (small),
263 0xFF, /* VGH1_L_DIV, VGL1_L_DIV (1.5MHz) */
264 0xFF, /* VGH1_R_DIV, VGL1_R_DIV (1.5MHz) */
265 0xCC, /* VGH2_L_DIV, VGL2_L_DIV (2.6MHz) */
266 0xCC, /* VGH2_R_DIV, VGL2_R_DIV (2.6MHz) */
267 0x77, /* VGH3_L_DIV, VGL3_L_DIV (4.5MHz) */
268 0x77 /* VGH3_R_DIV, VGL3_R_DIV (4.5MHz) */);
272 0x07, /* VREF_SEL = 4.2V */
273 0x07 /* NVREF_SEL = 4.2V */);
276 0x2C, /* VCOMDC_F = -0.67V */
277 0x2C /* VCOMDC_B = -0.67V */);
280 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
284 0x82, 0x10, 0x06, 0x05, 0xA2, 0x0A, 0xA5, 0x12,
285 0x31, 0x23, 0x37, 0x83, 0x04, 0xBC, 0x27, 0x38,
286 0x0C, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0C, 0x00,
287 0x03, 0x00, 0x00, 0x00, 0x75, 0x75, 0x31, 0x88,
288 0x88, 0x88, 0x88, 0x88, 0x88, 0x13, 0x88, 0x64,
289 0x64, 0x20, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
290 0x02, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
291 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
295 0x02, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
296 0x00, 0x00, 0x00, 0x00, 0x02, 0x46, 0x02, 0x88,
297 0x88, 0x88, 0x88, 0x88, 0x88, 0x64, 0x88, 0x13,
298 0x57, 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x88,
299 0x75, 0x88, 0x23, 0x14, 0x00, 0x00, 0x02, 0x00,
300 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
301 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0A,
302 0xA5, 0x00, 0x00, 0x00, 0x00);
306 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41, 0x35,
307 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12, 0x12,
308 0x18, 0x00, 0x09, 0x0D, 0x23, 0x27, 0x3C, 0x41,
309 0x35, 0x07, 0x0D, 0x0E, 0x12, 0x13, 0x10, 0x12,
310 0x12, 0x18);
342 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
343 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00,
344 0xda, 0x80);
345 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0x70);
346 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
347 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
348 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
349 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a);
350 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x92, 0x92);
351 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22,
352 0xf0, 0x63);
353 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05,
354 0xf9, 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00,
355 0x00, 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a,
356 0x00, 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
357 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47);
358 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
359 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
360 0x00, 0x00, 0x12, 0x50, 0x00);
361 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0xc0, 0x32,
362 0x32, 0x77, 0xe1, 0xdd, 0xdd, 0x77, 0x77, 0x33,
363 0x33);
364 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
365 0x00, 0xff);
366 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
367 0x00, 0x00);
368 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
369 0x02);
370 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b);
371 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0d,
372 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c, 0x0d,
373 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a, 0x00, 0x07,
374 0x0d, 0x37, 0x35, 0x3f, 0x41, 0x44, 0x06, 0x0c,
375 0x0d, 0x0f, 0x11, 0x10, 0x12, 0x14, 0x1a);
376 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
377 0x0b, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
378 0xc0, 0x10);
379 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x02, 0x00,
380 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x80,
381 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00,
382 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,
383 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88,
384 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35,
385 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
386 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
387 0x00, 0x00, 0x00);
388 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
389 0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
390 0x81, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88,
391 0x88, 0x88, 0x88, 0x80, 0x88, 0xba, 0x06, 0x42,
392 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00,
393 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
394 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
395 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
396 0x00);
397 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
435 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
436 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9,
437 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
438 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00,
439 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
440 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0,
441 0x63);
442 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
443 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
444 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
445 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
446 0x00, 0x00, 0x12, 0x70, 0x00);
447 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46);
448 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b);
449 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
450 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x3c, 0x12, 0x30);
451 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
452 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
453 0xc0, 0x10);
454 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x36, 0x00, 0x32,
455 0x32, 0x77, 0xf1, 0xcc, 0xcc, 0x77, 0x77, 0x33,
456 0x33);
457 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x0a, 0x0a);
458 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x88, 0x88);
459 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x0a, 0x10,
460 0x0f, 0xa1, 0x80, 0x12, 0x31, 0x23, 0x47, 0x86,
461 0xa1, 0x80, 0x47, 0x08, 0x00, 0x00, 0x0d, 0x00,
462 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00,
463 0x48, 0x02, 0x8b, 0xaf, 0x46, 0x02, 0x88, 0x88,
464 0x88, 0x88, 0x88, 0x48, 0x13, 0x8b, 0xaf, 0x57,
465 0x13, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
467 0x00, 0x00, 0x00);
468 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x96, 0x12, 0x01, 0x01,
469 0x01, 0x78, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
470 0x4f, 0x31, 0x8b, 0xa8, 0x31, 0x75, 0x88, 0x88,
471 0x88, 0x88, 0x88, 0x4f, 0x20, 0x8b, 0xa8, 0x20,
472 0x64, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x00,
473 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
474 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
475 0x00, 0x00, 0x40, 0xa1, 0x80, 0x00, 0x00, 0x00,
476 0x00);
477 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x0a, 0x0f,
478 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d, 0x10,
479 0x13, 0x15, 0x14, 0x15, 0x10, 0x17, 0x00, 0x0a,
480 0x0f, 0x29, 0x3b, 0x3f, 0x42, 0x39, 0x06, 0x0d,
481 0x10, 0x13, 0x15, 0x14, 0x15, 0x10, 0x17);
512 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
513 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETAPID, 0x00, 0x00, 0x00, 0xda,
514 0x80);
515 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0xc8, 0x02, 0x30);
516 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x10, 0x10, 0x28,
517 0x28, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
518 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
519 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x04, 0x04);
520 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x78, 0x78);
521 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25, 0x22, 0xf0,
522 0x63);
523 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x33, 0x81, 0x05, 0xf9,
524 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
525 0x00, 0x00, 0x44, 0x25, 0x00, 0x90, 0x0a, 0x00,
526 0x00, 0x01, 0x4f, 0x01, 0x00, 0x00, 0x37);
527 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x47);
528 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
529 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
530 0x00, 0x00, 0x12, 0x70, 0x00);
531 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x25, 0x00, 0x32,
532 0x32, 0x77, 0xe1, 0xff, 0xff, 0xcc, 0xcc, 0x77,
533 0x77);
534 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETECO, 0x82, 0x00, 0xbf, 0xff,
535 0x00, 0xff);
536 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETIO, 0xb8, 0x00, 0x0a, 0x00,
537 0x00, 0x00);
538 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCABC, 0x10, 0x40, 0x1e,
539 0x02);
540 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b);
541 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x04, 0x07,
542 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b, 0x0e,
543 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17, 0x00, 0x04,
544 0x07, 0x2a, 0x39, 0x3f, 0x36, 0x31, 0x06, 0x0b,
545 0x0e, 0x12, 0x14, 0x12, 0x13, 0x0f, 0x17);
546 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x03, 0x03, 0x03, 0x03,
547 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0xff, 0x80,
548 0xc0, 0x10);
549 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0xc8, 0x10, 0x08, 0x00,
550 0x00, 0x41, 0xf8, 0x12, 0x31, 0x23, 0x37, 0x86,
551 0x11, 0xc8, 0x37, 0x2a, 0x00, 0x00, 0x0c, 0x00,
552 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00,
553 0x88, 0x20, 0x46, 0x02, 0x88, 0x88, 0x88, 0x88,
554 0x88, 0x88, 0xff, 0x88, 0x31, 0x57, 0x13, 0x88,
555 0x88, 0x88, 0x88, 0x88, 0x88, 0xff, 0x00, 0x00,
556 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
557 0x00, 0x00, 0x00);
558 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x00, 0x1a, 0x00, 0x00,
559 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
560 0x8f, 0x13, 0x31, 0x75, 0x88, 0x88, 0x88, 0x88,
561 0x88, 0x88, 0xf8, 0x8f, 0x02, 0x20, 0x64, 0x88,
562 0x88, 0x88, 0x88, 0x88, 0x88, 0xf8, 0x00, 0x00,
563 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
564 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
565 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
566 0x00);
567 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_EF, 0xff, 0xff, 0x01);
604 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEXTC, 0xf1, 0x12, 0x83);
605 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETMIPI, 0x31, 0x81, 0x05, 0xf9,
606 0x0e, 0x0e, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
607 0x00, 0x00, 0x44, 0x25, 0x00, 0x91, 0x0a, 0x00,
608 0x00, 0x02, 0x4f, 0xd1, 0x00, 0x00, 0x37);
609 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER_EXT, 0x25);
610 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_UNKNOWN_BF, 0x02, 0x11, 0x00);
611 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETRGBIF, 0x0c, 0x10, 0x0a,
612 0x50, 0x03, 0xff, 0x00, 0x00, 0x00, 0x00);
613 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETSCR, 0x73, 0x73, 0x50, 0x50,
614 0x00, 0x00, 0x08, 0x70, 0x00);
615 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVDC, 0x46);
616 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPANEL, 0x0b);
617 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETCYC, 0x80);
618 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETDISP, 0x00, 0x13, 0xf0);
619 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETEQ, 0x07, 0x07, 0x0b, 0x0b,
620 0x03, 0x0b, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00,
621 0xc0, 0x10);
622 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETPOWER, 0x53, 0x00, 0x1e,
623 0x1e, 0x77, 0xe1, 0xcc, 0xdd, 0x67, 0x77, 0x33,
624 0x33);
625 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETBGP, 0x10, 0x10);
626 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETVCOM, 0x6c, 0x7c);
627 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP1, 0x08, 0x00, 0x0e, 0x00,
628 0x00, 0xb0, 0xb1, 0x11, 0x31, 0x23, 0x28, 0x10,
629 0xb0, 0xb1, 0x27, 0x08, 0x00, 0x04, 0x02, 0x00,
630 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0x00,
631 0x88, 0x88, 0xba, 0x60, 0x24, 0x08, 0x88, 0x88,
632 0x88, 0x88, 0x88, 0x88, 0x88, 0xba, 0x71, 0x35,
633 0x18, 0x88, 0x88, 0x88, 0x88, 0x88, 0x00, 0x00,
634 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
635 0x00, 0x00, 0x00);
636 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGIP2, 0x97, 0x0a, 0x82, 0x02,
637 0x13, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
638 0x80, 0x88, 0xba, 0x17, 0x53, 0x88, 0x88, 0x88,
639 0x88, 0x88, 0x88, 0x81, 0x88, 0xba, 0x06, 0x42,
640 0x88, 0x88, 0x88, 0x88, 0x88, 0x88, 0x23, 0x10,
641 0x00, 0x02, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
642 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
643 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
644 0x00);
645 mipi_dsi_dcs_write_seq_multi(dsi_ctx, ST7703_CMD_SETGAMMA, 0x00, 0x07, 0x0b,
646 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0x0a, 0x0b,
647 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18, 0x00, 0x07,
648 0x0b, 0x27, 0x2d, 0x3f, 0x3b, 0x37, 0x05, 0xa0,
649 0x0b, 0x0f, 0x11, 0x0f, 0x12, 0x12, 0x18);
721 return 0;
733 if (ret < 0) {
739 if (ret < 0) {
748 gpiod_set_value_cansleep(ctx->reset_gpio, 0);
751 return 0;
878 if (ret < 0)
888 if (ret < 0) {
900 return 0;
909 if (ret < 0)