Lines Matching +full:0 +full:xe8
23 #define ST7701_CMD2BKX_SEL 0xFF
24 #define ST7701_CMD1 0
26 #define ST7701_CMD2BK_MASK GENMASK(3, 0)
29 #define ST7701_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
30 #define ST7701_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
31 #define ST7701_CMD2_BK0_LNESET 0xC0 /* Display Line setting */
32 #define ST7701_CMD2_BK0_PORCTRL 0xC1 /* Porch control */
33 #define ST7701_CMD2_BK0_INVSEL 0xC2 /* Inversion selection, Frame Rate Control */
36 #define ST7701_CMD2_BK1_VRHS 0xB0 /* Vop amplitude setting */
37 #define ST7701_CMD2_BK1_VCOM 0xB1 /* VCOM amplitude setting */
38 #define ST7701_CMD2_BK1_VGHSS 0xB2 /* VGH Voltage setting */
39 #define ST7701_CMD2_BK1_TESTCMD 0xB3 /* TEST Command Setting */
40 #define ST7701_CMD2_BK1_VGLS 0xB5 /* VGL Voltage setting */
41 #define ST7701_CMD2_BK1_PWCTLR1 0xB7 /* Power Control 1 */
42 #define ST7701_CMD2_BK1_PWCTLR2 0xB8 /* Power Control 2 */
43 #define ST7701_CMD2_BK1_SPD1 0xC1 /* Source pre_drive timing set1 */
44 #define ST7701_CMD2_BK1_SPD2 0xC2 /* Source EQ2 Setting */
45 #define ST7701_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
49 #define ST7701_CMD2_BK0_GAMCTRL_VC0_MASK GENMASK(3, 0)
50 #define ST7701_CMD2_BK0_GAMCTRL_VC4_MASK GENMASK(5, 0)
51 #define ST7701_CMD2_BK0_GAMCTRL_VC8_MASK GENMASK(5, 0)
52 #define ST7701_CMD2_BK0_GAMCTRL_VC16_MASK GENMASK(4, 0)
53 #define ST7701_CMD2_BK0_GAMCTRL_VC24_MASK GENMASK(4, 0)
54 #define ST7701_CMD2_BK0_GAMCTRL_VC52_MASK GENMASK(3, 0)
55 #define ST7701_CMD2_BK0_GAMCTRL_VC80_MASK GENMASK(5, 0)
56 #define ST7701_CMD2_BK0_GAMCTRL_VC108_MASK GENMASK(3, 0)
57 #define ST7701_CMD2_BK0_GAMCTRL_VC147_MASK GENMASK(3, 0)
58 #define ST7701_CMD2_BK0_GAMCTRL_VC175_MASK GENMASK(5, 0)
59 #define ST7701_CMD2_BK0_GAMCTRL_VC203_MASK GENMASK(3, 0)
60 #define ST7701_CMD2_BK0_GAMCTRL_VC231_MASK GENMASK(4, 0)
61 #define ST7701_CMD2_BK0_GAMCTRL_VC239_MASK GENMASK(4, 0)
62 #define ST7701_CMD2_BK0_GAMCTRL_VC247_MASK GENMASK(5, 0)
63 #define ST7701_CMD2_BK0_GAMCTRL_VC251_MASK GENMASK(5, 0)
64 #define ST7701_CMD2_BK0_GAMCTRL_VC255_MASK GENMASK(4, 0)
65 #define ST7701_CMD2_BK0_LNESET_LINE_MASK GENMASK(6, 0)
67 #define ST7701_CMD2_BK0_LNESET_LINEDELTA GENMASK(1, 0)
68 #define ST7701_CMD2_BK0_PORCTRL_VBP_MASK GENMASK(7, 0)
69 #define ST7701_CMD2_BK0_PORCTRL_VFP_MASK GENMASK(7, 0)
71 #define ST7701_CMD2_BK0_INVSEL_NLINV_MASK GENMASK(2, 0)
72 #define ST7701_CMD2_BK0_INVSEL_RTNI_MASK GENMASK(4, 0)
75 #define ST7701_CMD2_BK1_VRHA_MASK GENMASK(7, 0)
76 #define ST7701_CMD2_BK1_VCOM_MASK GENMASK(7, 0)
77 #define ST7701_CMD2_BK1_VGHSS_MASK GENMASK(3, 0)
80 #define ST7701_CMD2_BK1_VGLS_MASK GENMASK(3, 0)
83 #define ST7701_CMD2_BK1_PWRCTRL1_APOS_MASK GENMASK(1, 0)
85 #define ST7701_CMD2_BK1_PWRCTRL2_AVCL_MASK GENMASK(1, 0)
87 #define ST7701_CMD2_BK1_SPD1_T2D_MASK GENMASK(3, 0)
89 #define ST7701_CMD2_BK1_SPD2_T3D_MASK GENMASK(3, 0)
97 OP_BIAS_OFF = 0,
177 { -7060, 0x0 }, { -7470, 0x1 },
178 { -7910, 0x2 }, { -8140, 0x3 },
179 { -8650, 0x4 }, { -8920, 0x5 },
180 { -9210, 0x6 }, { -9510, 0x7 },
181 { -9830, 0x8 }, { -10170, 0x9 },
182 { -10530, 0xa }, { -10910, 0xb },
183 { -11310, 0xc }, { -11730, 0xd },
184 { -12200, 0xe }, { -12690, 0xf }
188 for (i = 0; i < ARRAY_SIZE(map); i++)
192 return 0;
204 ST7701_WRITE(st7701, ST7701_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, val);
214 ST7701_WRITE(st7701, MIPI_DCS_SOFT_RESET, 0x00);
219 ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
224 st7701_switch_cmd_bkx(st7701, true, 0);
232 * Line[6:0]: select number of vertical lines of the TFT matrix in
235 * Line_delta[1:0]: add 0/2/4/6 extra lines to line count selected
236 * using Line[6:0]
239 * LN = ((Line[6:0] + 1) * 8) + (LDE_EN ? Line_delta[1:0] * 2 : 0)
243 (linecountrem2 ? ST7701_CMD2_BK0_LNESET_LDE_EN : 0),
252 * PCLK = 512 + (RTNI[4:0] * 16)
265 /* Vop = 3.5375V + (VRHA[7:0] * 0.0125V) */
270 /* Vcom = 0.1V + (VCOM[7:0] * 0.0125V) */
275 /* Vgh = 11.5V + (VGHSS[7:0] * 0.5V) */
298 /* Avdd = 6.2V + (AVDD[1:0] * 0.2V) , Avcl = -4.4V - (AVCL[1:0] * 0.2V) */
305 /* T2D = 0.2us * T2D[3:0] */
311 /* T3D = 4us + (0.8us * T3D[3:0]) */
319 (desc->eot_en ? ST7701_CMD2_BK1_MIPISET1_EOT_EN : 0));
328 ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
329 ST7701_WRITE(st7701, 0xE1, 0x0B, 0x00, 0x0D, 0x00, 0x0C, 0x00, 0x0E,
330 0x00, 0x00, 0x44, 0x44);
331 ST7701_WRITE(st7701, 0xE2, 0x33, 0x33, 0x44, 0x44, 0x64, 0x00, 0x66,
332 0x00, 0x65, 0x00, 0x67, 0x00, 0x00);
333 ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
334 ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
335 ST7701_WRITE(st7701, 0xE5, 0x0C, 0x78, 0x3C, 0xA0, 0x0E, 0x78, 0x3C,
336 0xA0, 0x10, 0x78, 0x3C, 0xA0, 0x12, 0x78, 0x3C, 0xA0);
337 ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
338 ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
339 ST7701_WRITE(st7701, 0xE8, 0x0D, 0x78, 0x3C, 0xA0, 0x0F, 0x78, 0x3C,
340 0xA0, 0x11, 0x78, 0x3C, 0xA0, 0x13, 0x78, 0x3C, 0xA0);
341 ST7701_WRITE(st7701, 0xEB, 0x02, 0x02, 0x39, 0x39, 0xEE, 0x44, 0x00);
342 ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);
343 ST7701_WRITE(st7701, 0xED, 0xFF, 0xF1, 0x04, 0x56, 0x72, 0x3F, 0xFF,
344 0xFF, 0xFF, 0xFF, 0xF3, 0x27, 0x65, 0x40, 0x1F, 0xFF);
349 ST7701_WRITE(st7701, 0xEE, 0x42);
350 ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
352 ST7701_WRITE(st7701, 0xE1,
353 0x04, 0xA0, 0x06, 0xA0,
354 0x05, 0xA0, 0x07, 0xA0,
355 0x00, 0x44, 0x44);
356 ST7701_WRITE(st7701, 0xE2,
357 0x00, 0x00, 0x00, 0x00,
358 0x00, 0x00, 0x00, 0x00,
359 0x00, 0x00, 0x00, 0x00);
360 ST7701_WRITE(st7701, 0xE3,
361 0x00, 0x00, 0x22, 0x22);
362 ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
363 ST7701_WRITE(st7701, 0xE5,
364 0x0C, 0x90, 0xA0, 0xA0,
365 0x0E, 0x92, 0xA0, 0xA0,
366 0x08, 0x8C, 0xA0, 0xA0,
367 0x0A, 0x8E, 0xA0, 0xA0);
368 ST7701_WRITE(st7701, 0xE6,
369 0x00, 0x00, 0x22, 0x22);
370 ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
371 ST7701_WRITE(st7701, 0xE8,
372 0x0D, 0x91, 0xA0, 0xA0,
373 0x0F, 0x93, 0xA0, 0xA0,
374 0x09, 0x8D, 0xA0, 0xA0,
375 0x0B, 0x8F, 0xA0, 0xA0);
376 ST7701_WRITE(st7701, 0xEB,
377 0x00, 0x00, 0xE4, 0xE4,
378 0x44, 0x00, 0x00);
379 ST7701_WRITE(st7701, 0xED,
380 0xFF, 0xF5, 0x47, 0x6F,
381 0x0B, 0xA1, 0xAB, 0xFF,
382 0xFF, 0xBA, 0x1A, 0xB0,
383 0xF6, 0x74, 0x5F, 0xFF);
384 ST7701_WRITE(st7701, 0xEF,
385 0x08, 0x08, 0x08, 0x40,
386 0x3F, 0x64);
388 st7701_switch_cmd_bkx(st7701, false, 0);
391 ST7701_WRITE(st7701, 0xE6, 0x7C);
392 ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);
394 st7701_switch_cmd_bkx(st7701, false, 0);
395 ST7701_WRITE(st7701, 0x11);
399 ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);
401 ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
403 st7701_switch_cmd_bkx(st7701, false, 0);
404 ST7701_WRITE(st7701, 0x11);
406 ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
408 st7701_switch_cmd_bkx(st7701, false, 0);
410 ST7701_WRITE(st7701, 0x3A, 0x70);
419 ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
420 ST7701_WRITE(st7701, 0xE1, 0x08, 0x00, 0x0A, 0x00, 0x07, 0x00, 0x09,
421 0x00, 0x00, 0x33, 0x33);
422 ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
423 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
424 ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x33);
425 ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
426 ST7701_WRITE(st7701, 0xE5, 0x0E, 0x60, 0xA0, 0xA0, 0x10, 0x60, 0xA0,
427 0xA0, 0x0A, 0x60, 0xA0, 0xA0, 0x0C, 0x60, 0xA0, 0xA0);
428 ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x33);
429 ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
430 ST7701_WRITE(st7701, 0xE8, 0x0D, 0x60, 0xA0, 0xA0, 0x0F, 0x60, 0xA0,
431 0xA0, 0x09, 0x60, 0xA0, 0xA0, 0x0B, 0x60, 0xA0, 0xA0);
432 ST7701_WRITE(st7701, 0xEB, 0x02, 0x01, 0xE4, 0xE4, 0x44, 0x00, 0x40);
433 ST7701_WRITE(st7701, 0xEC, 0x02, 0x01);
434 ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x01, 0xFF, 0xFF,
435 0xFF, 0xFF, 0xFF, 0xFF, 0x10, 0x45, 0x67, 0x98, 0xBA);
441 ST7701_WRITE(st7701, 0xEF, 0x08);
442 st7701_switch_cmd_bkx(st7701, true, 0);
443 ST7701_WRITE(st7701, 0xC7, 0x04);
444 ST7701_WRITE(st7701, 0xCC, 0x38);
446 ST7701_WRITE(st7701, 0xB9, 0x10);
447 ST7701_WRITE(st7701, 0xBC, 0x03);
448 ST7701_WRITE(st7701, 0xC0, 0x89);
449 ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
450 ST7701_WRITE(st7701, 0xE1, 0x04, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00,
451 0x00, 0x00, 0x20, 0x20);
452 ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
453 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
454 ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x33, 0x00);
455 ST7701_WRITE(st7701, 0xE4, 0x22, 0x00);
456 ST7701_WRITE(st7701, 0xE5, 0x04, 0x5C, 0xA0, 0xA0, 0x06, 0x5C, 0xA0,
457 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
458 ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x33, 0x00);
459 ST7701_WRITE(st7701, 0xE7, 0x22, 0x00);
460 ST7701_WRITE(st7701, 0xE8, 0x05, 0x5C, 0xA0, 0xA0, 0x07, 0x5C, 0xA0,
461 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
462 ST7701_WRITE(st7701, 0xEB, 0x02, 0x00, 0x40, 0x40, 0x00, 0x00, 0x00);
463 ST7701_WRITE(st7701, 0xEC, 0x00, 0x00);
464 ST7701_WRITE(st7701, 0xED, 0xFA, 0x45, 0x0B, 0xFF, 0xFF, 0xFF, 0xFF,
465 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xB0, 0x54, 0xAF);
466 ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
467 st7701_switch_cmd_bkx(st7701, false, 0);
468 ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x17);
469 ST7701_WRITE(st7701, MIPI_DCS_SET_PIXEL_FORMAT, 0x77);
470 ST7701_WRITE(st7701, MIPI_DCS_EXIT_SLEEP_MODE, 0x00);
477 ST7701_WRITE(st7701, 0xEF, 0x08);
479 st7701_switch_cmd_bkx(st7701, true, 0);
480 ST7701_WRITE(st7701, 0xC3, 0x02, 0x10, 0x02);
481 ST7701_WRITE(st7701, 0xC7, 0x04);
482 ST7701_WRITE(st7701, 0xCC, 0x10);
485 ST7701_WRITE(st7701, 0xEE, 0x42);
486 ST7701_WRITE(st7701, 0xE0, 0x00, 0x00, 0x02);
488 ST7701_WRITE(st7701, 0xE1, 0x04, 0xA0, 0x06, 0xA0, 0x05, 0xA0, 0x07, 0xA0,
489 0x00, 0x44, 0x44);
490 ST7701_WRITE(st7701, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
491 0x00, 0x00, 0x00, 0x00);
492 ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x22, 0x22);
493 ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
494 ST7701_WRITE(st7701, 0xE5, 0x0C, 0x90, 0xA0, 0xA0, 0x0E, 0x92, 0xA0, 0xA0,
495 0x08, 0x8C, 0xA0, 0xA0, 0x0A, 0x8E, 0xA0, 0xA0);
496 ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x22, 0x22);
497 ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
498 ST7701_WRITE(st7701, 0xE8, 0x0D, 0x91, 0xA0, 0xA0, 0x0F, 0x93, 0xA0, 0xA0,
499 0x09, 0x8D, 0xA0, 0xA0, 0x0B, 0x8F, 0xA0, 0xA0);
500 ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x44, 0x00, 0x40);
501 ST7701_WRITE(st7701, 0xED, 0xFF, 0xF5, 0x47, 0x6F, 0x0B, 0xA1, 0xBA, 0xFF,
502 0xFF, 0xAB, 0x1A, 0xB0, 0xF6, 0x74, 0x5F, 0xFF);
503 ST7701_WRITE(st7701, 0xEF, 0x08, 0x08, 0x08, 0x45, 0x3F, 0x54);
505 st7701_switch_cmd_bkx(st7701, false, 0);
508 ST7701_WRITE(st7701, 0xE6, 0x16);
509 ST7701_WRITE(st7701, 0xE8, 0x00, 0x0E);
511 st7701_switch_cmd_bkx(st7701, false, 0);
512 ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0x10);
517 ST7701_WRITE(st7701, 0xE8, 0x00, 0x0C);
519 ST7701_WRITE(st7701, 0xE8, 0x00, 0x00);
520 st7701_switch_cmd_bkx(st7701, false, 0);
525 ST7701_WRITE(st7701, 0xE0, 0x00, 0x28, 0x02);
526 ST7701_WRITE(st7701, 0xE1, 0x08, 0xA0, 0x00, 0x00, 0x07, 0xA0, 0x00,
527 0x00, 0x00, 0x44, 0x44);
528 ST7701_WRITE(st7701, 0xE2, 0x11, 0x11, 0x44, 0x44, 0xED, 0xA0, 0x00,
529 0x00, 0xEC, 0xA0, 0x00, 0x00);
530 ST7701_WRITE(st7701, 0xE3, 0x00, 0x00, 0x11, 0x11);
531 ST7701_WRITE(st7701, 0xE4, 0x44, 0x44);
532 ST7701_WRITE(st7701, 0xE5, 0x0A, 0xE9, 0xD8, 0xA0, 0x0C, 0xEB, 0xD8,
533 0xA0, 0x0E, 0xED, 0xD8, 0xA0, 0x10, 0xEF, 0xD8, 0xA0);
534 ST7701_WRITE(st7701, 0xE6, 0x00, 0x00, 0x11, 0x11);
535 ST7701_WRITE(st7701, 0xE7, 0x44, 0x44);
536 ST7701_WRITE(st7701, 0xE8, 0x09, 0xE8, 0xD8, 0xA0, 0x0B, 0xEA, 0xD8,
537 0xA0, 0x0D, 0xEC, 0xD8, 0xA0, 0x0F, 0xEE, 0xD8, 0xA0);
538 ST7701_WRITE(st7701, 0xEB, 0x00, 0x00, 0xE4, 0xE4, 0x88, 0x00, 0x40);
539 ST7701_WRITE(st7701, 0xEC, 0x3C, 0x00);
540 ST7701_WRITE(st7701, 0xED, 0xAB, 0x89, 0x76, 0x54, 0x02, 0xFF, 0xFF,
541 0xFF, 0xFF, 0xFF, 0xFF, 0x20, 0x45, 0x67, 0x98, 0xBA);
542 ST7701_WRITE(st7701, MIPI_DCS_SET_ADDRESS_MODE, 0);
550 gpiod_set_value(st7701->reset, 0);
554 if (ret < 0)
567 st7701_switch_cmd_bkx(st7701, false, 0);
569 return 0;
576 ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_ON, 0x00);
578 return 0;
585 ST7701_WRITE(st7701, MIPI_DCS_SET_DISPLAY_OFF, 0x00);
587 return 0;
594 ST7701_WRITE(st7701, MIPI_DCS_ENTER_SLEEP_MODE, 0x00);
598 gpiod_set_value(st7701->reset, 0);
613 return 0;
688 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
689 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
690 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
691 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
692 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
693 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
694 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
696 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
697 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
698 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x8),
699 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x8),
700 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
702 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
703 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x23),
704 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
705 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
706 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
708 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
709 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
710 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2b),
711 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
712 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
713 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
714 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
717 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
718 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
719 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
720 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xe),
721 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x2) |
722 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x15),
723 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xf),
725 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
726 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x13),
727 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x7),
728 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x9),
729 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
731 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
732 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
733 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
734 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
735 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x10),
737 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
738 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
739 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x2c),
740 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
741 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x34),
742 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
743 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
789 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
790 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
791 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
792 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
793 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
794 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
795 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
797 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
798 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
799 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
800 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
801 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
803 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
804 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
805 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
806 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
807 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
809 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
810 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
811 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
812 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
813 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
814 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
815 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
818 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
819 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
820 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
821 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
822 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
823 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
824 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
826 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
827 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
828 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
829 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
830 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
832 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
833 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
834 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
835 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
836 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
838 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
839 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
840 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
841 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
842 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
843 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
844 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
885 .panel_sleep_delay = 0,
888 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
889 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
890 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
891 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
892 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
893 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
894 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
896 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
897 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
898 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
899 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x2),
900 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
902 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
903 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1e),
904 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
905 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
906 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
908 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
910 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x23),
911 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
912 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
913 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
914 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
917 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
918 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
919 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
920 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xc),
921 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
922 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
923 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xc),
925 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
926 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
927 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x5),
928 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x3),
929 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
931 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
932 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
933 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
934 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
935 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
937 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x11),
939 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x24),
940 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
941 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
942 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
943 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x18)
987 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
988 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
989 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
990 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
991 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
992 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1d),
993 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
995 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
996 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x12),
997 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
998 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
999 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0a),
1001 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
1002 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x25),
1003 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
1004 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1005 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x03),
1007 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
1008 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1009 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
1010 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1011 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
1012 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1013 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
1016 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0x01) |
1017 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1018 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1019 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x16),
1020 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1021 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1e),
1022 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0e),
1024 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1025 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1026 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x06),
1027 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x0c),
1028 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
1030 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x09),
1031 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x26),
1032 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x00),
1033 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1034 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x15),
1036 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x00),
1037 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1038 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x3f),
1039 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1040 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3f),
1041 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1042 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1c)
1044 .nlinv = 0,
1087 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1088 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1089 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1090 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x10),
1091 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1092 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x17),
1093 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xd),
1095 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1096 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1097 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1098 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x5),
1099 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1101 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x7),
1102 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x1f),
1103 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x4),
1104 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1105 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x11),
1107 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0xe),
1108 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1109 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x29),
1110 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1111 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1112 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1113 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1116 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1117 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0),
1118 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1119 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0xd),
1120 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1121 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x14),
1122 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0xe),
1124 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1125 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x11),
1126 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x6),
1127 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x4),
1128 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x8),
1130 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x8),
1131 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x20),
1132 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x5),
1133 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1134 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x13),
1136 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x13),
1137 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1138 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0x26),
1139 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1140 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x30),
1141 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1142 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1185 .panel_sleep_delay = 0,
1188 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1189 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC0_MASK, 0x1),
1190 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1191 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x08),
1192 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1193 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x10),
1194 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0c),
1196 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1197 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x10),
1198 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x08),
1199 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x10),
1200 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x0c),
1202 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x08),
1203 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
1204 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x04),
1205 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1206 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0x14),
1208 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x12),
1209 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1210 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0xb3),
1211 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1212 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x3a),
1213 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1214 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x1f)
1217 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1218 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x13),
1219 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1220 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC4_MASK, 0x19),
1221 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1222 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC8_MASK, 0x1f),
1223 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC16_MASK, 0x0f),
1225 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1226 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC24_MASK, 0x14),
1227 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC52_MASK, 0x07),
1228 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC80_MASK, 0x07),
1229 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC108_MASK, 0x08),
1231 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC147_MASK, 0x07),
1232 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC175_MASK, 0x22),
1233 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC203_MASK, 0x02),
1234 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1235 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC231_MASK, 0xf),
1237 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC239_MASK, 0x0f),
1238 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1239 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC247_MASK, 0xa3),
1240 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1241 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC251_MASK, 0x29),
1242 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_AJ_MASK, 0) |
1243 CFIELD_PREP(ST7701_CMD2_BK0_GAMCTRL_VC255_MASK, 0x0d)
1285 st7701->supplies[0].supply = "VCC";
1290 if (ret < 0)
1300 if (ret < 0)
1353 return 0;
1378 return 0;
1445 return 0;