1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)  in hdmi_wp_dump()  argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))  in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)  in hdmi_wp_get_irqstatus()  argument
46 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)  in hdmi_wp_set_irqstatus()  argument
51 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);  in hdmi_wp_set_irqstatus()
53 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_set_irqenable()  argument
58 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);  in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_clear_irqenable()  argument
63 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);  in hdmi_wp_clear_irqenable()
67 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)  in hdmi_wp_set_phy_pwr()  argument
70 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)  in hdmi_wp_set_phy_pwr()
74 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);  in hdmi_wp_set_phy_pwr()
77 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)  in hdmi_wp_set_phy_pwr()
80 		return -ETIMEDOUT;  in hdmi_wp_set_phy_pwr()
87 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)  in hdmi_wp_set_pll_pwr()  argument
90 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);  in hdmi_wp_set_pll_pwr()
93 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)  in hdmi_wp_set_pll_pwr()
96 		return -ETIMEDOUT;  in hdmi_wp_set_pll_pwr()
102 int hdmi_wp_video_start(struct hdmi_wp_data *wp)  in hdmi_wp_video_start()  argument
104 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);  in hdmi_wp_video_start()
109 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)  in hdmi_wp_video_stop()  argument
113 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);  in hdmi_wp_video_stop()
115 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);  in hdmi_wp_video_stop()
122 		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);  in hdmi_wp_video_stop()
127 	DSSERR("no HDMI FRAMEDONE when disabling output\n");  in hdmi_wp_video_stop()
130 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_format()  argument
135 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,  in hdmi_wp_video_config_format()
138 	l |= FLD_VAL(video_fmt->y_res, 31, 16);  in hdmi_wp_video_config_format()
139 	l |= FLD_VAL(video_fmt->x_res, 15, 0);  in hdmi_wp_video_config_format()
140 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);  in hdmi_wp_video_config_format()
143 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_interface()  argument
150 	vsync_inv = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW);  in hdmi_wp_video_config_interface()
151 	hsync_inv = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW);  in hdmi_wp_video_config_interface()
153 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);  in hdmi_wp_video_config_interface()
158 	r = FLD_MOD(r, !!(vm->flags & DISPLAY_FLAGS_INTERLACED), 3, 3);  in hdmi_wp_video_config_interface()
160 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);  in hdmi_wp_video_config_interface()
163 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_timing()  argument
174 	 * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsync_len-1.  in hdmi_wp_video_config_timing()
178 	if (wp->version == 4)  in hdmi_wp_video_config_timing()
181 	timing_h |= FLD_VAL(vm->hback_porch, 31, 20);  in hdmi_wp_video_config_timing()
182 	timing_h |= FLD_VAL(vm->hfront_porch, 19, 8);  in hdmi_wp_video_config_timing()
183 	timing_h |= FLD_VAL(vm->hsync_len - hsync_len_offset, 7, 0);  in hdmi_wp_video_config_timing()
184 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);  in hdmi_wp_video_config_timing()
186 	timing_v |= FLD_VAL(vm->vback_porch, 31, 20);  in hdmi_wp_video_config_timing()
187 	timing_v |= FLD_VAL(vm->vfront_porch, 19, 8);  in hdmi_wp_video_config_timing()
188 	timing_v |= FLD_VAL(vm->vsync_len, 7, 0);  in hdmi_wp_video_config_timing()
189 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);  in hdmi_wp_video_config_timing()
197 	video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;  in hdmi_wp_init_vid_fmt_timings()
198 	video_fmt->y_res = param->vm.vactive;  in hdmi_wp_init_vid_fmt_timings()
199 	video_fmt->x_res = param->vm.hactive;  in hdmi_wp_init_vid_fmt_timings()
201 	vm->hback_porch = param->vm.hback_porch;  in hdmi_wp_init_vid_fmt_timings()
202 	vm->hfront_porch = param->vm.hfront_porch;  in hdmi_wp_init_vid_fmt_timings()
203 	vm->hsync_len = param->vm.hsync_len;  in hdmi_wp_init_vid_fmt_timings()
204 	vm->vback_porch = param->vm.vback_porch;  in hdmi_wp_init_vid_fmt_timings()
205 	vm->vfront_porch = param->vm.vfront_porch;  in hdmi_wp_init_vid_fmt_timings()
206 	vm->vsync_len = param->vm.vsync_len;  in hdmi_wp_init_vid_fmt_timings()
208 	vm->flags = param->vm.flags;  in hdmi_wp_init_vid_fmt_timings()
210 	if (param->vm.flags & DISPLAY_FLAGS_INTERLACED) {  in hdmi_wp_init_vid_fmt_timings()
211 		video_fmt->y_res /= 2;  in hdmi_wp_init_vid_fmt_timings()
212 		vm->vback_porch /= 2;  in hdmi_wp_init_vid_fmt_timings()
213 		vm->vfront_porch /= 2;  in hdmi_wp_init_vid_fmt_timings()
214 		vm->vsync_len /= 2;  in hdmi_wp_init_vid_fmt_timings()
217 	if (param->vm.flags & DISPLAY_FLAGS_DOUBLECLK) {  in hdmi_wp_init_vid_fmt_timings()
218 		video_fmt->x_res *= 2;  in hdmi_wp_init_vid_fmt_timings()
219 		vm->hfront_porch *= 2;  in hdmi_wp_init_vid_fmt_timings()
220 		vm->hsync_len *= 2;  in hdmi_wp_init_vid_fmt_timings()
221 		vm->hback_porch *= 2;  in hdmi_wp_init_vid_fmt_timings()
225 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_format()  argument
232 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);  in hdmi_wp_audio_config_format()
233 	if (wp->version == 4) {  in hdmi_wp_audio_config_format()
234 		r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);  in hdmi_wp_audio_config_format()
235 		r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);  in hdmi_wp_audio_config_format()
237 	r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);  in hdmi_wp_audio_config_format()
238 	r = FLD_MOD(r, aud_fmt->type, 4, 4);  in hdmi_wp_audio_config_format()
239 	r = FLD_MOD(r, aud_fmt->justification, 3, 3);  in hdmi_wp_audio_config_format()
240 	r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);  in hdmi_wp_audio_config_format()
241 	r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);  in hdmi_wp_audio_config_format()
242 	r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);  in hdmi_wp_audio_config_format()
243 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);  in hdmi_wp_audio_config_format()
246 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_dma()  argument
253 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);  in hdmi_wp_audio_config_dma()
254 	r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);  in hdmi_wp_audio_config_dma()
255 	r = FLD_MOD(r, aud_dma->block_size, 7, 0);  in hdmi_wp_audio_config_dma()
256 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);  in hdmi_wp_audio_config_dma()
258 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);  in hdmi_wp_audio_config_dma()
259 	r = FLD_MOD(r, aud_dma->mode, 9, 9);  in hdmi_wp_audio_config_dma()
260 	r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);  in hdmi_wp_audio_config_dma()
261 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);  in hdmi_wp_audio_config_dma()
264 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_enable()  argument
266 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);  in hdmi_wp_audio_enable()
271 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_core_req_enable()  argument
273 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);  in hdmi_wp_audio_core_req_enable()
278 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,  in hdmi_wp_init()  argument
283 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");  in hdmi_wp_init()
284 	wp->base = devm_ioremap_resource(&pdev->dev, res);  in hdmi_wp_init()
285 	if (IS_ERR(wp->base))  in hdmi_wp_init()
286 		return PTR_ERR(wp->base);  in hdmi_wp_init()
288 	wp->phys_base = res->start;  in hdmi_wp_init()
289 	wp->version = version;  in hdmi_wp_init()
294 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)  in hdmi_wp_get_audio_dma_addr()  argument
296 	return wp->phys_base + HDMI_WP_AUDIO_DATA;  in hdmi_wp_get_audio_dma_addr()