Lines Matching refs:wp
68 struct hdmi_wp_data *wp = &hdmi->wp;
71 irqstatus = hdmi_wp_get_irqstatus(wp);
72 hdmi_wp_set_irqstatus(wp, irqstatus);
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
96 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
99 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
104 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
106 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
172 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
173 hdmi_wp_set_irqstatus(&hdmi->wp,
174 hdmi_wp_get_irqstatus(&hdmi->wp));
195 r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);
199 hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
205 r = hdmi_wp_video_start(&hdmi->wp);
209 hdmi_wp_set_irqenable(&hdmi->wp,
217 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
229 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
231 hdmi_wp_video_stop(&hdmi->wp);
235 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
253 hdmi_wp_dump(&hdmi->wp, s);
265 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
266 hdmi_wp_audio_enable(&hd->wp, true);
267 hdmi_wp_audio_core_req_enable(&hd->wp, true);
272 hdmi_wp_audio_core_req_enable(&hd->wp, false);
273 hdmi_wp_audio_enable(&hd->wp, false);
274 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
390 ret = hdmi5_audio_config(&hdmi->core, &hdmi->wp,
449 idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
451 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
459 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
574 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
601 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
614 REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
632 r = hdmi_pll_init(dss, hdmi->pdev, &hdmi->pll, &hdmi->wp);
745 r = hdmi_wp_init(pdev, &hdmi->wp, 5);