Lines Matching +full:enum +full:- +full:model
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
64 enum omap_channel channel);
66 enum omap_channel channel,
67 enum dss_clk_source clk_src);
71 enum dss_model model; member
76 const enum omap_display_type *ports;
78 const enum omap_dss_output_id *outputs;
98 __raw_writel(val, dss->base + idx.idx); in dss_write_reg()
103 return __raw_readl(dss->base + idx.idx); in dss_read_reg()
107 dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
109 dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
117 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { in dss_save_context()
122 dss->ctx_valid = true; in dss_save_context()
131 if (!dss->ctx_valid) in dss_restore_context()
136 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { in dss_restore_context()
152 if (!pll->dss->syscon_pll_ctrl) in dss_ctrl_pll_enable()
157 switch (pll->id) { in dss_ctrl_pll_enable()
168 DSSERR("illegal DSS PLL ID %d\n", pll->id); in dss_ctrl_pll_enable()
172 regmap_update_bits(pll->dss->syscon_pll_ctrl, in dss_ctrl_pll_enable()
173 pll->dss->syscon_pll_ctrl_offset, in dss_ctrl_pll_enable()
178 enum dss_clk_source clk_src, in dss_ctrl_pll_set_control_mux()
179 enum omap_channel channel) in dss_ctrl_pll_set_control_mux()
183 if (!dss->syscon_pll_ctrl) in dss_ctrl_pll_set_control_mux()
184 return -EINVAL; in dss_ctrl_pll_set_control_mux()
197 return -EINVAL; in dss_ctrl_pll_set_control_mux()
213 return -EINVAL; in dss_ctrl_pll_set_control_mux()
229 return -EINVAL; in dss_ctrl_pll_set_control_mux()
235 return -EINVAL; in dss_ctrl_pll_set_control_mux()
238 regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset, in dss_ctrl_pll_set_control_mux()
252 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ in dss_sdi_init()
267 dispc_pck_free_enable(dss->dispc, 1); in dss_sdi_enable()
297 dispc_lcd_enable_signal(dss->dispc, 1); in dss_sdi_enable()
311 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_enable()
316 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_enable()
318 return -ETIMEDOUT; in dss_sdi_enable()
323 dispc_lcd_enable_signal(dss->dispc, 0); in dss_sdi_disable()
325 dispc_pck_free_enable(dss->dispc, 0); in dss_sdi_disable()
331 const char *dss_get_clk_source_name(enum dss_clk_source clk_src) in dss_get_clk_source_name()
344 seq_printf(s, "- DSS -\n"); in dss_dump_clocks()
347 fclk_rate = clk_get_rate(dss->dss_clk); in dss_dump_clocks()
358 struct dss_device *dss = s->private; in dss_dump_regs()
360 #define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r)) in dss_dump_regs()
370 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { in dss_dump_regs()
383 struct dss_device *dss = s->private; in dss_debug_dump_clocks()
386 dispc_dump_clocks(dss->dispc, s); in dss_debug_dump_clocks()
390 static int dss_get_channel_index(enum omap_channel channel) in dss_get_channel_index()
406 enum dss_clk_source clk_src) in dss_select_dispc_clk_source()
414 if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) in dss_select_dispc_clk_source()
433 dss->feat->dispc_clk_switch.start, in dss_select_dispc_clk_source()
434 dss->feat->dispc_clk_switch.end); in dss_select_dispc_clk_source()
436 dss->dispc_clk_source = clk_src; in dss_select_dispc_clk_source()
440 enum dss_clk_source clk_src) in dss_select_dsi_clk_source()
464 dss->dsi_clk_source[dsi_module] = clk_src; in dss_select_dsi_clk_source()
468 enum omap_channel channel, in dss_lcd_clk_mux_dra7()
469 enum dss_clk_source clk_src) in dss_lcd_clk_mux_dra7()
483 return -EINVAL; in dss_lcd_clk_mux_dra7()
496 enum omap_channel channel, in dss_lcd_clk_mux_omap5()
497 enum dss_clk_source clk_src) in dss_lcd_clk_mux_omap5()
504 const enum dss_clk_source allowed_plls[] = { in dss_lcd_clk_mux_omap5()
515 return -EINVAL; in dss_lcd_clk_mux_omap5()
519 return -EINVAL; in dss_lcd_clk_mux_omap5()
527 enum omap_channel channel, in dss_lcd_clk_mux_omap4()
528 enum dss_clk_source clk_src) in dss_lcd_clk_mux_omap4()
534 const enum dss_clk_source allowed_plls[] = { in dss_lcd_clk_mux_omap4()
548 return -EINVAL; in dss_lcd_clk_mux_omap4()
556 enum omap_channel channel, in dss_select_lcd_clk_source()
557 enum dss_clk_source clk_src) in dss_select_lcd_clk_source()
562 if (!dss->feat->has_lcd_clk_src) { in dss_select_lcd_clk_source()
564 dss->lcd_clk_source[idx] = clk_src; in dss_select_lcd_clk_source()
568 r = dss->feat->ops->select_lcd_source(dss, channel, clk_src); in dss_select_lcd_clk_source()
572 dss->lcd_clk_source[idx] = clk_src; in dss_select_lcd_clk_source()
575 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss) in dss_get_dispc_clk_source()
577 return dss->dispc_clk_source; in dss_get_dispc_clk_source()
580 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss, in dss_get_dsi_clk_source()
583 return dss->dsi_clk_source[dsi_module]; in dss_get_dsi_clk_source()
586 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss, in dss_get_lcd_clk_source()
587 enum omap_channel channel) in dss_get_lcd_clk_source()
589 if (dss->feat->has_lcd_clk_src) { in dss_get_lcd_clk_source()
591 return dss->lcd_clk_source[idx]; in dss_get_lcd_clk_source()
595 return dss->dispc_clk_source; in dss_get_lcd_clk_source()
609 fck_hw_max = dss->feat->fck_freq_max; in dss_div_calc()
611 if (dss->parent_clk == NULL) { in dss_div_calc()
618 fck = clk_round_rate(dss->dss_clk, fck); in dss_div_calc()
623 fckd_hw_max = dss->feat->fck_div_max; in dss_div_calc()
625 m = dss->feat->dss_fck_multiplier; in dss_div_calc()
626 prate = clk_get_rate(dss->parent_clk); in dss_div_calc()
633 for (fckd = fckd_start; fckd >= fckd_stop; --fckd) { in dss_div_calc()
649 r = clk_set_rate(dss->dss_clk, rate); in dss_set_fck_rate()
653 dss->dss_clk_rate = clk_get_rate(dss->dss_clk); in dss_set_fck_rate()
655 WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu", in dss_set_fck_rate()
656 dss->dss_clk_rate, rate); in dss_set_fck_rate()
663 return dss->dss_clk_rate; in dss_get_dispc_clk_rate()
668 return dss->feat->fck_freq_max; in dss_get_max_fck_rate()
678 max_dss_fck = dss->feat->fck_freq_max; in dss_setup_default_clock()
680 if (dss->parent_clk == NULL) { in dss_setup_default_clock()
681 fck = clk_round_rate(dss->dss_clk, max_dss_fck); in dss_setup_default_clock()
683 prate = clk_get_rate(dss->parent_clk); in dss_setup_default_clock()
685 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier, in dss_setup_default_clock()
688 * dss->feat->dss_fck_multiplier; in dss_setup_default_clock()
698 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type) in dss_set_venc_output()
715 /* DAC Power-Down Control */ in dss_set_dac_pwrdn_bgz()
720 enum dss_hdmi_venc_clk_source_select src) in dss_select_hdmi_venc_clk_source()
722 enum omap_dss_output_id outputs; in dss_select_hdmi_venc_clk_source()
724 outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; in dss_select_hdmi_venc_clk_source()
738 enum omap_channel channel) in dss_dpi_select_source_omap2_omap3()
741 return -EINVAL; in dss_dpi_select_source_omap2_omap3()
747 enum omap_channel channel) in dss_dpi_select_source_omap4()
759 return -EINVAL; in dss_dpi_select_source_omap4()
768 enum omap_channel channel) in dss_dpi_select_source_omap5()
786 return -EINVAL; in dss_dpi_select_source_omap5()
795 enum omap_channel channel) in dss_dpi_select_source_dra7xx()
802 return -EINVAL; in dss_dpi_select_source_dra7xx()
806 return -EINVAL; in dss_dpi_select_source_dra7xx()
809 return -EINVAL; in dss_dpi_select_source_dra7xx()
816 enum omap_channel channel) in dss_dpi_select_source()
818 return dss->feat->ops->dpi_select_source(dss, port, channel); in dss_dpi_select_source()
825 clk = devm_clk_get(&dss->pdev->dev, "fck"); in dss_get_clocks()
831 dss->dss_clk = clk; in dss_get_clocks()
833 if (dss->feat->parent_clk_name) { in dss_get_clocks()
834 clk = clk_get(NULL, dss->feat->parent_clk_name); in dss_get_clocks()
837 dss->feat->parent_clk_name); in dss_get_clocks()
844 dss->parent_clk = clk; in dss_get_clocks()
851 if (dss->parent_clk) in dss_put_clocks()
852 clk_put(dss->parent_clk); in dss_put_clocks()
861 r = pm_runtime_get_sync(&dss->pdev->dev); in dss_runtime_get()
863 pm_runtime_put_noidle(&dss->pdev->dev); in dss_runtime_get()
875 r = pm_runtime_put_sync(&dss->pdev->dev); in dss_runtime_put()
876 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); in dss_runtime_put()
894 dss->debugfs.root = dir; in dss_initialize_debugfs()
901 debugfs_remove_recursive(dss->debugfs.root); in dss_uninitialize_debugfs()
912 struct dss_debugfs_entry *entry = inode->i_private; in dss_debug_open()
914 return single_open(file, entry->show_fn, entry->data); in dss_debug_open()
933 return ERR_PTR(-ENOMEM); in dss_debugfs_create_file()
935 entry->show_fn = show_fn; in dss_debugfs_create_file()
936 entry->data = data; in dss_debugfs_create_file()
937 entry->dentry = debugfs_create_file(name, 0444, dss->debugfs.root, in dss_debugfs_create_file()
948 debugfs_remove(entry->dentry); in dss_debugfs_remove_file()
981 static const enum omap_display_type omap2plus_ports[] = {
985 static const enum omap_display_type omap34xx_ports[] = {
990 static const enum omap_display_type dra7xx_ports[] = {
996 static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
1004 static const enum omap_dss_output_id omap3430_dss_supported_outputs[] = {
1013 static const enum omap_dss_output_id omap3630_dss_supported_outputs[] = {
1022 static const enum omap_dss_output_id am43xx_dss_supported_outputs[] = {
1027 static const enum omap_dss_output_id omap4_dss_supported_outputs[] = {
1039 static const enum omap_dss_output_id omap5_dss_supported_outputs[] = {
1057 .model = DSS_MODEL_OMAP2,
1075 .model = DSS_MODEL_OMAP3,
1089 .model = DSS_MODEL_OMAP3,
1103 .model = DSS_MODEL_OMAP4,
1117 .model = DSS_MODEL_OMAP5,
1131 .model = DSS_MODEL_OMAP3,
1145 .model = DSS_MODEL_DRA7,
1160 struct platform_device *pdev = dss->pdev; in __dss_uninit_ports()
1161 struct device_node *parent = pdev->dev.of_node; in __dss_uninit_ports()
1170 switch (dss->feat->ports[i]) { in __dss_uninit_ports()
1186 struct platform_device *pdev = dss->pdev; in dss_init_ports()
1187 struct device_node *parent = pdev->dev.of_node; in dss_init_ports()
1192 for (i = 0; i < dss->feat->num_ports; i++) { in dss_init_ports()
1197 switch (dss->feat->ports[i]) { in dss_init_ports()
1199 r = dpi_init_port(dss, pdev, port, dss->feat->model); in dss_init_ports()
1226 __dss_uninit_ports(dss, dss->feat->num_ports); in dss_uninit_ports()
1231 struct platform_device *pdev = dss->pdev; in dss_video_pll_probe()
1232 struct device_node *np = pdev->dev.of_node; in dss_video_pll_probe()
1239 if (of_property_read_bool(np, "syscon-pll-ctrl")) { in dss_video_pll_probe()
1240 dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, in dss_video_pll_probe()
1241 "syscon-pll-ctrl"); in dss_video_pll_probe()
1242 if (IS_ERR(dss->syscon_pll_ctrl)) { in dss_video_pll_probe()
1243 dev_err(&pdev->dev, in dss_video_pll_probe()
1244 "failed to get syscon-pll-ctrl regmap\n"); in dss_video_pll_probe()
1245 return PTR_ERR(dss->syscon_pll_ctrl); in dss_video_pll_probe()
1248 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, in dss_video_pll_probe()
1249 &dss->syscon_pll_ctrl_offset)) { in dss_video_pll_probe()
1250 dev_err(&pdev->dev, in dss_video_pll_probe()
1251 "failed to get syscon-pll-ctrl offset\n"); in dss_video_pll_probe()
1252 return -EINVAL; in dss_video_pll_probe()
1256 pll_regulator = devm_regulator_get(&pdev->dev, "vdda_video"); in dss_video_pll_probe()
1261 case -ENOENT: in dss_video_pll_probe()
1265 case -EPROBE_DEFER: in dss_video_pll_probe()
1266 return -EPROBE_DEFER; in dss_video_pll_probe()
1274 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { in dss_video_pll_probe()
1275 dss->video1_pll = dss_video_pll_init(dss, pdev, 0, in dss_video_pll_probe()
1277 if (IS_ERR(dss->video1_pll)) in dss_video_pll_probe()
1278 return PTR_ERR(dss->video1_pll); in dss_video_pll_probe()
1281 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { in dss_video_pll_probe()
1282 dss->video2_pll = dss_video_pll_init(dss, pdev, 1, in dss_video_pll_probe()
1284 if (IS_ERR(dss->video2_pll)) { in dss_video_pll_probe()
1285 dss_video_pll_uninit(dss->video1_pll); in dss_video_pll_probe()
1286 return PTR_ERR(dss->video2_pll); in dss_video_pll_probe()
1295 { .compatible = "ti,omap2-dss", .data = &omap24xx_dss_feats },
1296 { .compatible = "ti,omap3-dss", .data = &omap3630_dss_feats },
1297 { .compatible = "ti,omap4-dss", .data = &omap44xx_dss_feats },
1298 { .compatible = "ti,omap5-dss", .data = &omap54xx_dss_feats },
1299 { .compatible = "ti,dra7-dss", .data = &dra7xx_dss_feats },
1332 dss->drm_pdev = drm_pdev; in dss_bind()
1341 platform_device_unregister(dss->drm_pdev); in dss_unbind()
1359 struct component_match **match = cmatch->match; in dss_add_child_component()
1376 if (strstr(dev_name(dev), "target-module")) in dss_add_child_component()
1380 component_match_add(cmatch->dev, match, component_compare_dev, dev); in dss_add_child_component()
1394 dss->dss_clk_rate = clk_get_rate(dss->dss_clk); in dss_probe_hardware()
1406 dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK; in dss_probe_hardware()
1407 dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK; in dss_probe_hardware()
1408 dss->dispc_clk_source = DSS_CLK_SRC_FCK; in dss_probe_hardware()
1409 dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK; in dss_probe_hardware()
1410 dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK; in dss_probe_hardware()
1430 return -ENOMEM; in dss_probe()
1432 dss->pdev = pdev; in dss_probe()
1435 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); in dss_probe()
1437 dev_err(&pdev->dev, "Failed to set the DMA mask\n"); in dss_probe()
1442 * The various OMAP3-based SoCs can't be told apart using the compatible in dss_probe()
1447 dss->feat = soc->data; in dss_probe()
1449 dss->feat = device_get_match_data(&pdev->dev); in dss_probe()
1452 dss->base = devm_platform_ioremap_resource(pdev, 0); in dss_probe()
1453 if (IS_ERR(dss->base)) { in dss_probe()
1454 r = PTR_ERR(dss->base); in dss_probe()
1476 pm_runtime_enable(&pdev->dev); in dss_probe()
1487 dss->debugfs.clk = dss_debugfs_create_file(dss, "clk", in dss_probe()
1489 dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs, in dss_probe()
1493 r = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); in dss_probe()
1497 omapdss_gather_components(&pdev->dev); in dss_probe()
1499 cmatch.dev = &pdev->dev; in dss_probe()
1501 device_for_each_child(&pdev->dev, &cmatch, dss_add_child_component); in dss_probe()
1503 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); in dss_probe()
1510 of_platform_depopulate(&pdev->dev); in dss_probe()
1513 dss_debugfs_remove_file(dss->debugfs.clk); in dss_probe()
1514 dss_debugfs_remove_file(dss->debugfs.dss); in dss_probe()
1518 pm_runtime_disable(&pdev->dev); in dss_probe()
1522 if (dss->video1_pll) in dss_probe()
1523 dss_video_pll_uninit(dss->video1_pll); in dss_probe()
1524 if (dss->video2_pll) in dss_probe()
1525 dss_video_pll_uninit(dss->video2_pll); in dss_probe()
1540 of_platform_depopulate(&pdev->dev); in dss_remove()
1542 component_master_del(&pdev->dev, &dss_component_ops); in dss_remove()
1544 dss_debugfs_remove_file(dss->debugfs.clk); in dss_remove()
1545 dss_debugfs_remove_file(dss->debugfs.dss); in dss_remove()
1548 pm_runtime_disable(&pdev->dev); in dss_remove()
1552 if (dss->video1_pll) in dss_remove()
1553 dss_video_pll_uninit(dss->video1_pll); in dss_remove()
1555 if (dss->video2_pll) in dss_remove()
1556 dss_video_pll_uninit(dss->video2_pll); in dss_remove()