Lines Matching refs:REG_GET
50 #define REG_GET(dsi, idx, start, end) \ macro
146 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
153 if (REG_GET(dsi, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1259 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
1730 return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0); in dsi_vc_is_enabled()
1741 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit) == 0) in dsi_packet_sent_handler_vp()
1763 if (REG_GET(dsi, DSI_VC_TE(vc), bit, bit)) { in dsi_sync_vc_vp()
1790 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0) in dsi_packet_sent_handler_l4()
1809 if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) { in dsi_sync_vc_l4()
1903 if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable) in dsi_vc_enable_hs()
1921 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { in dsi_vc_flush_long_data()
1972 while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { in dsi_vc_flush_receive_data()
2006 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { in dsi_vc_send_bta()
2222 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) { in dsi_vc_write_common()
2239 if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) { in dsi_vc_read_rx_fifo()
5007 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); in dsi_probe()