11 #define DISPC_REVISION			0x0000
12 #define DISPC_SYSCONFIG			0x0010
13 #define DISPC_SYSSTATUS			0x0014
14 #define DISPC_IRQSTATUS			0x0018
15 #define DISPC_IRQENABLE			0x001C
16 #define DISPC_CONTROL			0x0040
17 #define DISPC_CONFIG			0x0044
18 #define DISPC_CAPABLE			0x0048
19 #define DISPC_LINE_STATUS		0x005C
20 #define DISPC_LINE_NUMBER		0x0060
21 #define DISPC_GLOBAL_ALPHA		0x0074
22 #define DISPC_CONTROL2			0x0238
23 #define DISPC_CONFIG2			0x0620
24 #define DISPC_DIVISOR			0x0804
25 #define DISPC_GLOBAL_BUFFER		0x0800
26 #define DISPC_CONTROL3                  0x0848
27 #define DISPC_CONFIG3                   0x084C
28 #define DISPC_MSTANDBY_CTRL		0x0858
29 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE	0x085C
31 #define DISPC_GAMMA_TABLE0		0x0630
32 #define DISPC_GAMMA_TABLE1		0x0634
33 #define DISPC_GAMMA_TABLE2		0x0638
34 #define DISPC_GAMMA_TABLE3		0x0850
113 		return 0x004C;  in DISPC_DEFAULT_COLOR()
115 		return 0x0050;  in DISPC_DEFAULT_COLOR()
117 		return 0x03AC;  in DISPC_DEFAULT_COLOR()
119 		return 0x0814;  in DISPC_DEFAULT_COLOR()
122 		return 0;  in DISPC_DEFAULT_COLOR()
130 		return 0x0054;  in DISPC_TRANS_COLOR()
132 		return 0x0058;  in DISPC_TRANS_COLOR()
134 		return 0x03B0;  in DISPC_TRANS_COLOR()
136 		return 0x0818;  in DISPC_TRANS_COLOR()
139 		return 0;  in DISPC_TRANS_COLOR()
147 		return 0x0064;  in DISPC_TIMING_H()
150 		return 0;  in DISPC_TIMING_H()
152 		return 0x0400;  in DISPC_TIMING_H()
154 		return 0x0840;  in DISPC_TIMING_H()
157 		return 0;  in DISPC_TIMING_H()
165 		return 0x0068;  in DISPC_TIMING_V()
168 		return 0;  in DISPC_TIMING_V()
170 		return 0x0404;  in DISPC_TIMING_V()
172 		return 0x0844;  in DISPC_TIMING_V()
175 		return 0;  in DISPC_TIMING_V()
183 		return 0x006C;  in DISPC_POL_FREQ()
186 		return 0;  in DISPC_POL_FREQ()
188 		return 0x0408;  in DISPC_POL_FREQ()
190 		return 0x083C;  in DISPC_POL_FREQ()
193 		return 0;  in DISPC_POL_FREQ()
201 		return 0x0070;  in DISPC_DIVISORo()
204 		return 0;  in DISPC_DIVISORo()
206 		return 0x040C;  in DISPC_DIVISORo()
208 		return 0x0838;  in DISPC_DIVISORo()
211 		return 0;  in DISPC_DIVISORo()
220 		return 0x007C;  in DISPC_SIZE_MGR()
222 		return 0x0078;  in DISPC_SIZE_MGR()
224 		return 0x03CC;  in DISPC_SIZE_MGR()
226 		return 0x0834;  in DISPC_SIZE_MGR()
229 		return 0;  in DISPC_SIZE_MGR()
237 		return 0x01D4;  in DISPC_DATA_CYCLE1()
240 		return 0;  in DISPC_DATA_CYCLE1()
242 		return 0x03C0;  in DISPC_DATA_CYCLE1()
244 		return 0x0828;  in DISPC_DATA_CYCLE1()
247 		return 0;  in DISPC_DATA_CYCLE1()
255 		return 0x01D8;  in DISPC_DATA_CYCLE2()
258 		return 0;  in DISPC_DATA_CYCLE2()
260 		return 0x03C4;  in DISPC_DATA_CYCLE2()
262 		return 0x082C;  in DISPC_DATA_CYCLE2()
265 		return 0;  in DISPC_DATA_CYCLE2()
273 		return 0x01DC;  in DISPC_DATA_CYCLE3()
276 		return 0;  in DISPC_DATA_CYCLE3()
278 		return 0x03C8;  in DISPC_DATA_CYCLE3()
280 		return 0x0830;  in DISPC_DATA_CYCLE3()
283 		return 0;  in DISPC_DATA_CYCLE3()
291 		return 0x0220;  in DISPC_CPR_COEF_R()
294 		return 0;  in DISPC_CPR_COEF_R()
296 		return 0x03BC;  in DISPC_CPR_COEF_R()
298 		return 0x0824;  in DISPC_CPR_COEF_R()
301 		return 0;  in DISPC_CPR_COEF_R()
309 		return 0x0224;  in DISPC_CPR_COEF_G()
312 		return 0;  in DISPC_CPR_COEF_G()
314 		return 0x03B8;  in DISPC_CPR_COEF_G()
316 		return 0x0820;  in DISPC_CPR_COEF_G()
319 		return 0;  in DISPC_CPR_COEF_G()
327 		return 0x0228;  in DISPC_CPR_COEF_B()
330 		return 0;  in DISPC_CPR_COEF_B()
332 		return 0x03B4;  in DISPC_CPR_COEF_B()
334 		return 0x081C;  in DISPC_CPR_COEF_B()
337 		return 0;  in DISPC_CPR_COEF_B()
346 		return 0x0080;  in DISPC_OVL_BASE()
348 		return 0x00BC;  in DISPC_OVL_BASE()
350 		return 0x014C;  in DISPC_OVL_BASE()
352 		return 0x0300;  in DISPC_OVL_BASE()
354 		return 0x0500;  in DISPC_OVL_BASE()
357 		return 0;  in DISPC_OVL_BASE()
368 		return 0x0000;  in DISPC_BA0_OFFSET()
371 		return 0x0008;  in DISPC_BA0_OFFSET()
374 		return 0;  in DISPC_BA0_OFFSET()
384 		return 0x0004;  in DISPC_BA1_OFFSET()
387 		return 0x000C;  in DISPC_BA1_OFFSET()
390 		return 0;  in DISPC_BA1_OFFSET()
399 		return 0;  in DISPC_BA0_UV_OFFSET()
401 		return 0x0544;  in DISPC_BA0_UV_OFFSET()
403 		return 0x04BC;  in DISPC_BA0_UV_OFFSET()
405 		return 0x0310;  in DISPC_BA0_UV_OFFSET()
407 		return 0x0118;  in DISPC_BA0_UV_OFFSET()
410 		return 0;  in DISPC_BA0_UV_OFFSET()
419 		return 0;  in DISPC_BA1_UV_OFFSET()
421 		return 0x0548;  in DISPC_BA1_UV_OFFSET()
423 		return 0x04C0;  in DISPC_BA1_UV_OFFSET()
425 		return 0x0314;  in DISPC_BA1_UV_OFFSET()
427 		return 0x011C;  in DISPC_BA1_UV_OFFSET()
430 		return 0;  in DISPC_BA1_UV_OFFSET()
440 		return 0x0008;  in DISPC_POS_OFFSET()
442 		return 0x009C;  in DISPC_POS_OFFSET()
445 		return 0;  in DISPC_POS_OFFSET()
455 		return 0x000C;  in DISPC_SIZE_OFFSET()
458 		return 0x00A8;  in DISPC_SIZE_OFFSET()
461 		return 0;  in DISPC_SIZE_OFFSET()
469 		return 0x0020;  in DISPC_ATTR_OFFSET()
472 		return 0x0010;  in DISPC_ATTR_OFFSET()
475 		return 0x0070;  in DISPC_ATTR_OFFSET()
478 		return 0;  in DISPC_ATTR_OFFSET()
487 		return 0;  in DISPC_ATTR2_OFFSET()
489 		return 0x0568;  in DISPC_ATTR2_OFFSET()
491 		return 0x04DC;  in DISPC_ATTR2_OFFSET()
493 		return 0x032C;  in DISPC_ATTR2_OFFSET()
495 		return 0x0310;  in DISPC_ATTR2_OFFSET()
498 		return 0;  in DISPC_ATTR2_OFFSET()
506 		return 0x0024;  in DISPC_FIFO_THRESH_OFFSET()
509 		return 0x0014;  in DISPC_FIFO_THRESH_OFFSET()
512 		return 0x008C;  in DISPC_FIFO_THRESH_OFFSET()
515 		return 0;  in DISPC_FIFO_THRESH_OFFSET()
523 		return 0x0028;  in DISPC_FIFO_SIZE_STATUS_OFFSET()
526 		return 0x0018;  in DISPC_FIFO_SIZE_STATUS_OFFSET()
529 		return 0x0088;  in DISPC_FIFO_SIZE_STATUS_OFFSET()
532 		return 0;  in DISPC_FIFO_SIZE_STATUS_OFFSET()
540 		return 0x002C;  in DISPC_ROW_INC_OFFSET()
543 		return 0x001C;  in DISPC_ROW_INC_OFFSET()
546 		return 0x00A4;  in DISPC_ROW_INC_OFFSET()
549 		return 0;  in DISPC_ROW_INC_OFFSET()
557 		return 0x0030;  in DISPC_PIX_INC_OFFSET()
560 		return 0x0020;  in DISPC_PIX_INC_OFFSET()
563 		return 0x0098;  in DISPC_PIX_INC_OFFSET()
566 		return 0;  in DISPC_PIX_INC_OFFSET()
574 		return 0x0034;  in DISPC_WINDOW_SKIP_OFFSET()
579 		return 0;  in DISPC_WINDOW_SKIP_OFFSET()
582 		return 0;  in DISPC_WINDOW_SKIP_OFFSET()
590 		return 0x0038;  in DISPC_TABLE_BA_OFFSET()
595 		return 0;  in DISPC_TABLE_BA_OFFSET()
598 		return 0;  in DISPC_TABLE_BA_OFFSET()
607 		return 0;  in DISPC_FIR_OFFSET()
610 		return 0x0024;  in DISPC_FIR_OFFSET()
613 		return 0x0090;  in DISPC_FIR_OFFSET()
616 		return 0;  in DISPC_FIR_OFFSET()
625 		return 0;  in DISPC_FIR2_OFFSET()
627 		return 0x0580;  in DISPC_FIR2_OFFSET()
629 		return 0x055C;  in DISPC_FIR2_OFFSET()
631 		return 0x0424;  in DISPC_FIR2_OFFSET()
633 		return 0x290;  in DISPC_FIR2_OFFSET()
636 		return 0;  in DISPC_FIR2_OFFSET()
645 		return 0;  in DISPC_PIC_SIZE_OFFSET()
648 		return 0x0028;  in DISPC_PIC_SIZE_OFFSET()
651 		return 0x0094;  in DISPC_PIC_SIZE_OFFSET()
654 		return 0;  in DISPC_PIC_SIZE_OFFSET()
664 		return 0;  in DISPC_ACCU0_OFFSET()
667 		return 0x002C;  in DISPC_ACCU0_OFFSET()
670 		return 0x0000;  in DISPC_ACCU0_OFFSET()
673 		return 0;  in DISPC_ACCU0_OFFSET()
682 		return 0;  in DISPC_ACCU2_0_OFFSET()
684 		return 0x0584;  in DISPC_ACCU2_0_OFFSET()
686 		return 0x0560;  in DISPC_ACCU2_0_OFFSET()
688 		return 0x0428;  in DISPC_ACCU2_0_OFFSET()
690 		return 0x0294;  in DISPC_ACCU2_0_OFFSET()
693 		return 0;  in DISPC_ACCU2_0_OFFSET()
702 		return 0;  in DISPC_ACCU1_OFFSET()
705 		return 0x0030;  in DISPC_ACCU1_OFFSET()
708 		return 0x0004;  in DISPC_ACCU1_OFFSET()
711 		return 0;  in DISPC_ACCU1_OFFSET()
720 		return 0;  in DISPC_ACCU2_1_OFFSET()
722 		return 0x0588;  in DISPC_ACCU2_1_OFFSET()
724 		return 0x0564;  in DISPC_ACCU2_1_OFFSET()
726 		return 0x042C;  in DISPC_ACCU2_1_OFFSET()
728 		return 0x0298;  in DISPC_ACCU2_1_OFFSET()
731 		return 0;  in DISPC_ACCU2_1_OFFSET()
735 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
741 		return 0;  in DISPC_FIR_COEF_H_OFFSET()
744 		return 0x0034 + i * 0x8;  in DISPC_FIR_COEF_H_OFFSET()
747 		return 0x0010 + i * 0x8;  in DISPC_FIR_COEF_H_OFFSET()
750 		return 0;  in DISPC_FIR_COEF_H_OFFSET()
754 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
760 		return 0;  in DISPC_FIR_COEF_H2_OFFSET()
762 		return 0x058C + i * 0x8;  in DISPC_FIR_COEF_H2_OFFSET()
764 		return 0x0568 + i * 0x8;  in DISPC_FIR_COEF_H2_OFFSET()
766 		return 0x0430 + i * 0x8;  in DISPC_FIR_COEF_H2_OFFSET()
768 		return 0x02A0 + i * 0x8;  in DISPC_FIR_COEF_H2_OFFSET()
771 		return 0;  in DISPC_FIR_COEF_H2_OFFSET()
775 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
781 		return 0;  in DISPC_FIR_COEF_HV_OFFSET()
784 		return 0x0038 + i * 0x8;  in DISPC_FIR_COEF_HV_OFFSET()
787 		return 0x0014 + i * 0x8;  in DISPC_FIR_COEF_HV_OFFSET()
790 		return 0;  in DISPC_FIR_COEF_HV_OFFSET()
794 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
800 		return 0;  in DISPC_FIR_COEF_HV2_OFFSET()
802 		return 0x0590 + i * 8;  in DISPC_FIR_COEF_HV2_OFFSET()
804 		return 0x056C + i * 0x8;  in DISPC_FIR_COEF_HV2_OFFSET()
806 		return 0x0434 + i * 0x8;  in DISPC_FIR_COEF_HV2_OFFSET()
808 		return 0x02A4 + i * 0x8;  in DISPC_FIR_COEF_HV2_OFFSET()
811 		return 0;  in DISPC_FIR_COEF_HV2_OFFSET()
815 /* coef index i = {0, 1, 2, 3, 4,} */
821 		return 0;  in DISPC_CONV_COEF_OFFSET()
826 		return 0x0074 + i * 0x4;  in DISPC_CONV_COEF_OFFSET()
829 		return 0;  in DISPC_CONV_COEF_OFFSET()
833 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
839 		return 0;  in DISPC_FIR_COEF_V_OFFSET()
841 		return 0x0124 + i * 0x4;  in DISPC_FIR_COEF_V_OFFSET()
843 		return 0x00B4 + i * 0x4;  in DISPC_FIR_COEF_V_OFFSET()
846 		return 0x0050 + i * 0x4;  in DISPC_FIR_COEF_V_OFFSET()
849 		return 0;  in DISPC_FIR_COEF_V_OFFSET()
853 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
859 		return 0;  in DISPC_FIR_COEF_V2_OFFSET()
861 		return 0x05CC + i * 0x4;  in DISPC_FIR_COEF_V2_OFFSET()
863 		return 0x05A8 + i * 0x4;  in DISPC_FIR_COEF_V2_OFFSET()
865 		return 0x0470 + i * 0x4;  in DISPC_FIR_COEF_V2_OFFSET()
867 		return 0x02E0 + i * 0x4;  in DISPC_FIR_COEF_V2_OFFSET()
870 		return 0;  in DISPC_FIR_COEF_V2_OFFSET()
878 		return 0x01AC;  in DISPC_PRELOAD_OFFSET()
880 		return 0x0174;  in DISPC_PRELOAD_OFFSET()
882 		return 0x00E8;  in DISPC_PRELOAD_OFFSET()
884 		return 0x00A0;  in DISPC_PRELOAD_OFFSET()
887 		return 0;  in DISPC_PRELOAD_OFFSET()
895 		return 0x0860;  in DISPC_MFLAG_THRESHOLD_OFFSET()
897 		return 0x0864;  in DISPC_MFLAG_THRESHOLD_OFFSET()
899 		return 0x0868;  in DISPC_MFLAG_THRESHOLD_OFFSET()
901 		return 0x086c;  in DISPC_MFLAG_THRESHOLD_OFFSET()
903 		return 0x0870;  in DISPC_MFLAG_THRESHOLD_OFFSET()
906 		return 0;  in DISPC_MFLAG_THRESHOLD_OFFSET()