Lines Matching +full:fifo +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/dma-mapping.h>
78 /* An unknown HW bug causing the normal FIFO thresholds not to work */
105 u16 width, u16 height, u16 out_width, u16 out_height,
110 u16 width, u16 height, u16 out_width, u16 out_height,
176 /* maps which plane is using a fifo. fifo-id -> plane-id */
358 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
363 return __raw_readl(dispc->base + idx); in dispc_read_reg()
371 return REG_GET(dispc, rfld->reg, rfld->high, rfld->low); in mgr_fld_read()
379 REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low); in mgr_fld_write()
384 return dispc->feat->num_ovls; in dispc_get_num_ovls()
389 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
396 BUG_ON(id >= dispc->feat->num_reg_fields); in dispc_get_reg_field()
398 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
399 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
407 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
408 if (dispc->feat->features[i] == id) in dispc_has_feature()
416 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
418 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
522 dispc->ctx_valid = true; in dispc_save_context()
533 if (!dispc->ctx_valid) in dispc_restore_context()
655 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
657 pm_runtime_put_noidle(&dispc->pdev->dev); in dispc_runtime_get()
669 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
670 WARN_ON(r < 0 && r != -ENOSYS); in dispc_runtime_put()
682 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
784 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
835 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
836 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
837 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
838 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
839 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
841 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
846 /* YUV -> RGB, ITU-R BT.601, full range */
849 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
854 /* YUV -> RGB, ITU-R BT.601, limited range */
857 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
862 /* YUV -> RGB, ITU-R BT.709, full range */
865 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
870 /* YUV -> RGB, ITU-R BT.709, limited range */
873 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
943 enum omap_plane_id plane, int width, in dispc_ovl_set_input_size() argument
946 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_input_size()
955 enum omap_plane_id plane, int width, in dispc_ovl_set_output_size() argument
962 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); in dispc_ovl_set_output_size()
1239 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1247 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1256 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1269 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1290 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | in dispc_mgr_set_cpr_coef()
1291 FLD_VAL(coefs->rb, 9, 0); in dispc_mgr_set_cpr_coef()
1292 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | in dispc_mgr_set_cpr_coef()
1293 FLD_VAL(coefs->gb, 9, 0); in dispc_mgr_set_cpr_coef()
1294 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | in dispc_mgr_set_cpr_coef()
1295 FLD_VAL(coefs->bb, 9, 0); in dispc_mgr_set_cpr_coef()
1330 enum omap_channel channel, u16 width, u16 height) in dispc_mgr_set_size() argument
1334 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1335 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1343 int fifo; in dispc_init_fifos() local
1348 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1352 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1353 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1356 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1359 * By default fifos are mapped directly to overlays, fifo 0 to in dispc_init_fifos()
1360 * ovl 0, fifo 1 to ovl 1, etc. in dispc_init_fifos()
1362 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1366 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo in dispc_init_fifos()
1369 * giving GFX plane a larger fifo. WB but should work fine with a in dispc_init_fifos()
1370 * smaller fifo. in dispc_init_fifos()
1372 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1384 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1385 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1389 * Setup default fifo thresholds. in dispc_init_fifos()
1402 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1418 int fifo; in dispc_ovl_get_fifo_size() local
1421 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1422 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1423 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1436 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1449 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", in dispc_ovl_set_fifo_threshold()
1467 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1479 * buffer_units, and the fifo thresholds must be buffer_unit aligned. in dispc_ovl_compute_fifo_thresholds()
1481 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1497 * We use the same low threshold for both fifomerge and non-fifomerge in dispc_ovl_compute_fifo_thresholds()
1499 * combined fifo size in dispc_ovl_compute_fifo_thresholds()
1503 *fifo_low = ovl_fifo_size - burst_size * 2; in dispc_ovl_compute_fifo_thresholds()
1504 *fifo_high = total_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1509 * in the FIFO to form a burst in dispc_ovl_compute_fifo_thresholds()
1514 *fifo_low = ovl_fifo_size - burst_size; in dispc_ovl_compute_fifo_thresholds()
1515 *fifo_high = total_fifo_size - buf_unit; in dispc_ovl_compute_fifo_thresholds()
1552 * As a work-around, set force MFLAG to always on. in dispc_init_mflag()
1560 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1577 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1579 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1716 { 0, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1717 { 1, 2, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1718 { -1, 1, 0, 1 , -1, 2, 0, 1 }, in dispc_ovl_set_accu_uv()
1719 { -1, 2, -1, 2 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1723 { 0, 1, 0, 1 , -3, 4, -1, 4 }, in dispc_ovl_set_accu_uv()
1724 { -1, 4, -3, 4 , 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1725 { -1, 1, 0, 1 , -1, 4, -3, 4 }, in dispc_ovl_set_accu_uv()
1726 { -3, 4, -3, 4 , -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1732 { -1, 1, 0, 1, 0, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1733 { 0, 1, 0, 1, -1, 1, 0, 1 }, in dispc_ovl_set_accu_uv()
1736 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_accu_uv()
1774 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; in dispc_ovl_set_accu_uv()
1775 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; in dispc_ovl_set_accu_uv()
1776 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; in dispc_ovl_set_accu_uv()
1777 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; in dispc_ovl_set_accu_uv()
1830 accu0 -= accu1; in dispc_ovl_set_scaling_common()
1856 if (!info->is_yuv) { in dispc_ovl_set_scaling_uv()
1948 /* Note: DSS HW rotates clockwise, DRM_MODE_ROTATE_* counter-clockwise */ in dispc_ovl_set_rotation_attrs()
2047 return 1 + (pixels - 1) * ps; in pixinc()
2049 return 1 - (-pixels + 1) * ps; in pixinc()
2054 static void calc_offset(u16 screen_width, u16 width, in calc_offset() argument
2064 DSSDBG("scrw %d, width %d\n", screen_width, width); in calc_offset()
2072 * YUV422 pixel size gives the correct TILER container width. in calc_offset()
2073 * However, 'width' is in pixels and multiplying it with YUV422 in calc_offset()
2077 width *= 2; in calc_offset()
2087 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + in calc_offset()
2101 u16 width, u16 height, u16 out_width, u16 out_height, in check_horiz_timing_omap3() argument
2110 nonactive = vm->hactive + vm->hfront_porch + vm->hsync_len + in check_horiz_timing_omap3()
2111 vm->hback_porch - out_width; in check_horiz_timing_omap3()
2116 if (out_width < width) in check_horiz_timing_omap3()
2118 blank = div_u64((u64)(vm->hback_porch + vm->hsync_len + vm->hfront_porch) * in check_horiz_timing_omap3()
2122 return -EINVAL; in check_horiz_timing_omap3()
2124 /* FIXME add checks for 3-tap filter once the limitations are known */ in check_horiz_timing_omap3()
2130 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2131 * during nonactive - pos_x period. in check_horiz_timing_omap3()
2133 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); in check_horiz_timing_omap3()
2134 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", in check_horiz_timing_omap3()
2135 val, max(0, ds - 2) * width); in check_horiz_timing_omap3()
2136 if (val < max(0, ds - 2) * width) in check_horiz_timing_omap3()
2137 return -EINVAL; in check_horiz_timing_omap3()
2142 * DS - 1 lines should be loaded during nonactive period. in check_horiz_timing_omap3()
2145 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", in check_horiz_timing_omap3()
2146 val, max(0, ds - 1) * width); in check_horiz_timing_omap3()
2147 if (val < max(0, ds - 1) * width) in check_horiz_timing_omap3()
2148 return -EINVAL; in check_horiz_timing_omap3()
2154 const struct videomode *vm, u16 width, in calc_core_clk_five_taps() argument
2161 if (height <= out_height && width <= out_width) in calc_core_clk_five_taps()
2165 unsigned int ppl = vm->hactive; in calc_core_clk_five_taps()
2175 tmp = (u64)pclk * (height - 2 * out_height) * out_width; in calc_core_clk_five_taps()
2176 do_div(tmp, 2 * out_height * (ppl - out_width)); in calc_core_clk_five_taps()
2181 if (width > out_width) { in calc_core_clk_five_taps()
2182 tmp = (u64)pclk * width; in calc_core_clk_five_taps()
2193 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width, in calc_core_clk_24xx() argument
2196 if (height > out_height && width > out_width) in calc_core_clk_24xx()
2202 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width, in calc_core_clk_34xx() argument
2212 if (width > 3 * out_width) in calc_core_clk_34xx()
2214 else if (width > 2 * out_width) in calc_core_clk_34xx()
2216 else if (width > out_width) in calc_core_clk_34xx()
2228 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width, in calc_core_clk_44xx() argument
2240 if (width > out_width) in calc_core_clk_44xx()
2241 return DIV_ROUND_UP(pclk, out_width) * width; in calc_core_clk_44xx()
2249 u16 width, u16 height, in dispc_ovl_calc_scaling_24xx() argument
2260 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2266 in_width = width / *decim_x; in dispc_ovl_calc_scaling_24xx()
2267 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2285 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2289 DSSERR("Cannot scale max input width exceeded\n"); in dispc_ovl_calc_scaling_24xx()
2290 return -EINVAL; in dispc_ovl_calc_scaling_24xx()
2298 u16 width, u16 height, in dispc_ovl_calc_scaling_34xx() argument
2308 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2312 in_width = width / *decim_x; in dispc_ovl_calc_scaling_34xx()
2325 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2361 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2367 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2372 DSSERR("width exceeds maximum width possible\n"); in dispc_ovl_calc_scaling_34xx()
2373 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2378 return -EINVAL; in dispc_ovl_calc_scaling_34xx()
2386 u16 width, u16 height, in dispc_ovl_calc_scaling_44xx() argument
2397 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2398 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2407 *decim_x = DIV_ROUND_UP(width, in_width_max); in dispc_ovl_calc_scaling_44xx()
2411 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2414 in_width = width / *decim_x; in dispc_ovl_calc_scaling_44xx()
2419 DSSERR("Cannot scale width exceeds max line width\n"); in dispc_ovl_calc_scaling_44xx()
2420 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2435 * be true also for 16-bit color formats. in dispc_ovl_calc_scaling_44xx()
2437 DSSERR("Not enough bandwidth, too much downscaling (x-decimation factor %d > 4)\n", *decim_x); in dispc_ovl_calc_scaling_44xx()
2439 return -EINVAL; in dispc_ovl_calc_scaling_44xx()
2442 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2449 return dispc->feat->overlay_caps[plane]; in dispc_ovl_get_caps()
2453 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2460 u16 width, u16 height, in dispc_ovl_calc_scaling() argument
2467 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2468 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2473 if (width == out_width && height == out_height) in dispc_ovl_calc_scaling()
2476 if (dispc->feat->supported_scaler_color_modes) { in dispc_ovl_calc_scaling()
2477 const u32 *modes = dispc->feat->supported_scaler_color_modes; in dispc_ovl_calc_scaling()
2486 return -EINVAL; in dispc_ovl_calc_scaling()
2503 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { in dispc_ovl_calc_scaling()
2505 return -EINVAL; in dispc_ovl_calc_scaling()
2509 return -EINVAL; in dispc_ovl_calc_scaling()
2520 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale); in dispc_ovl_calc_scaling()
2523 if (decim_x > *x_predecim || out_width > width * 8) in dispc_ovl_calc_scaling()
2524 return -EINVAL; in dispc_ovl_calc_scaling()
2527 return -EINVAL; in dispc_ovl_calc_scaling()
2529 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2537 …DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req cl… in dispc_ovl_calc_scaling()
2538 width, height, in dispc_ovl_calc_scaling()
2540 out_width / width, DIV_FRAC(out_width, width), in dispc_ovl_calc_scaling()
2544 width / decim_x, height / decim_y, in dispc_ovl_calc_scaling()
2545 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x), in dispc_ovl_calc_scaling()
2556 return -EINVAL; in dispc_ovl_calc_scaling()
2564 void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height) in dispc_ovl_get_max_size() argument
2566 *width = dispc->feat->ovl_width_max; in dispc_ovl_get_max_size()
2567 *height = dispc->feat->ovl_height_max; in dispc_ovl_get_max_size()
2575 u16 width, u16 height, in dispc_ovl_setup_common() argument
2594 u16 in_width = width; in dispc_ovl_setup_common()
2596 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); in dispc_ovl_setup_common()
2605 pclk = vm->pixelclock; in dispc_ovl_setup_common()
2608 return -EINVAL; in dispc_ovl_setup_common()
2610 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2611 DSSERR("input width %d is not even for YUV format\n", in_width); in dispc_ovl_setup_common()
2612 return -EINVAL; in dispc_ovl_setup_common()
2615 out_width = out_width == 0 ? width : out_width; in dispc_ovl_setup_common()
2634 return -EINVAL; in dispc_ovl_setup_common()
2650 if (info->is_yuv && (in_width & 1)) { in dispc_ovl_setup_common()
2651 DSSDBG("predecimated input width is not even for YUV format\n"); in dispc_ovl_setup_common()
2652 DSSDBG("adjusting input width %d -> %d\n", in dispc_ovl_setup_common()
2658 if (info->is_yuv) in dispc_ovl_setup_common()
2702 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2713 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2714 row_inc += pix_inc - 1; in dispc_ovl_setup_common()
2719 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, in dispc_ovl_setup_common()
2756 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2759 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" in dispc_ovl_setup()
2761 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x, in dispc_ovl_setup()
2762 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, in dispc_ovl_setup()
2763 oi->fourcc, oi->rotation, channel, replication); in dispc_ovl_setup()
2767 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2768 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, in dispc_ovl_setup()
2769 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, in dispc_ovl_setup()
2770 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, in dispc_ovl_setup()
2771 oi->rotation_type, replication, vm, mem_to_mem, in dispc_ovl_setup()
2772 oi->color_encoding, oi->color_range); in dispc_ovl_setup()
2872 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
2873 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
2874 info->trans_key); in dispc_mgr_setup()
2875 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
2877 info->partial_alpha_enabled); in dispc_mgr_setup()
2879 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
2880 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
2951 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
2953 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
2954 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
2956 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
2958 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
2960 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
2966 u16 width, u16 height) in _dispc_mgr_size_ok() argument
2968 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
2969 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
2976 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
2977 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
2978 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
2979 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
2980 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
2981 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
2991 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
2993 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3000 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3003 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3008 if (vm->flags & DISPLAY_FLAGS_INTERLACED) in dispc_mgr_check_timings()
3011 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3012 vm->hfront_porch, vm->hback_porch, in dispc_mgr_check_timings()
3013 vm->vsync_len, vm->vfront_porch, in dispc_mgr_check_timings()
3014 vm->vback_porch)) in dispc_mgr_check_timings()
3028 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3029 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3030 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3031 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3032 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3033 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3038 vs = !!(vm->flags & DISPLAY_FLAGS_VSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3039 hs = !!(vm->flags & DISPLAY_FLAGS_HSYNC_LOW); in _dispc_mgr_set_lcd_timings()
3040 de = !!(vm->flags & DISPLAY_FLAGS_DE_LOW); in _dispc_mgr_set_lcd_timings()
3041 ipc = !!(vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE); in _dispc_mgr_set_lcd_timings()
3043 rf = !!(vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE); in _dispc_mgr_set_lcd_timings()
3053 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3058 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3073 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3084 return -1; in vm_flag_to_int()
3110 ht = vm->pixelclock / xtot; in dispc_mgr_set_timings()
3111 vt = vm->pixelclock / xtot / ytot; in dispc_mgr_set_timings()
3113 DSSDBG("pck %lu\n", vm->pixelclock); in dispc_mgr_set_timings()
3129 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3150 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3168 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3171 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3176 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3179 r = pll->cinfo.clkout[clkout_idx]; in dispc_fclk_rate()
3196 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3199 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3204 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3207 r = pll->cinfo.clkout[clkout_idx]; in dispc_mgr_lclk_rate()
3232 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3238 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3243 return dispc->core_clk_rate; in dispc_core_clk_rate()
3279 seq_printf(s, "- %s -\n", mgr_desc[channel].name); in dispc_dump_clocks_channel()
3281 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3288 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks_channel()
3290 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", in dispc_dump_clocks_channel()
3303 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3305 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3309 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3312 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3316 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", in dispc_dump_clocks()
3332 struct dispc_device *dispc = s->private; in dispc_dump_regs()
3350 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3384 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ in dispc_dump_regs()
3453 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3488 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ in dispc_dump_regs()
3534 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) in dispc_calc_clock_rates()
3535 return -EINVAL; in dispc_calc_clock_rates()
3536 if (cinfo->pck_div < 1 || cinfo->pck_div > 255) in dispc_calc_clock_rates()
3537 return -EINVAL; in dispc_calc_clock_rates()
3539 cinfo->lck = dispc_fclk_rate / cinfo->lck_div; in dispc_calc_clock_rates()
3540 cinfo->pck = cinfo->lck / cinfo->pck_div; in dispc_calc_clock_rates()
3563 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3566 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3609 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); in dispc_mgr_set_clock_div()
3610 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); in dispc_mgr_set_clock_div()
3612 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3613 cinfo->pck_div); in dispc_mgr_set_clock_div()
3655 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3658 return gdesc->len; in dispc_mgr_gamma_size()
3665 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3670 for (i = 0; i < gdesc->len; ++i) { in dispc_mgr_write_gamma_table()
3673 if (gdesc->has_index) in dispc_mgr_write_gamma_table()
3678 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3686 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3711 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3715 channel, length, gdesc->len); in dispc_mgr_set_gamma()
3717 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3725 for (i = 0; i < length - 1; ++i) { in dispc_mgr_set_gamma()
3726 uint first = i * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3727 uint last = (i + 1) * (gdesc->len - 1) / (length - 1); in dispc_mgr_set_gamma()
3728 uint w = last - first; in dispc_mgr_set_gamma()
3736 r = (lut[i].red * (w - j) + lut[i+1].red * j) / w; in dispc_mgr_set_gamma()
3737 g = (lut[i].green * (w - j) + lut[i+1].green * j) / w; in dispc_mgr_set_gamma()
3738 b = (lut[i].blue * (w - j) + lut[i+1].blue * j) / w; in dispc_mgr_set_gamma()
3740 r >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3741 g >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3742 b >>= 16 - gdesc->bits; in dispc_mgr_set_gamma()
3744 table[first + j] = (r << (gdesc->bits * 2)) | in dispc_mgr_set_gamma()
3745 (g << gdesc->bits) | b; in dispc_mgr_set_gamma()
3749 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3757 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3760 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3772 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3775 return -ENOMEM; in dispc_init_gamma_tables()
3777 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3796 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3800 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3804 * func-clock auto-gating. For newer versions in _omap_dispc_initial_config()
3805 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. in _omap_dispc_initial_config()
3808 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3819 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
4110 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4111 * cannot scale an image width larger than 768.
4369 if (!dispc->is_enabled) in dispc_irq_handler()
4372 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4380 if (dispc->user_handler != NULL) in dispc_request_irq()
4381 return -EBUSY; in dispc_request_irq()
4383 dispc->user_handler = handler; in dispc_request_irq()
4384 dispc->user_data = dev_id; in dispc_request_irq()
4389 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4392 dispc->user_handler = NULL; in dispc_request_irq()
4393 dispc->user_data = NULL; in dispc_request_irq()
4401 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4403 dispc->user_handler = NULL; in dispc_free_irq()
4404 dispc->user_data = NULL; in dispc_free_irq()
4412 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4420 * - LCD1 Gamma Correction Is Not Working When GFX Pipe Is Disabled
4454 .width = 1, .height = 1,
4491 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4494 i734_buf.size = i734.ovli.width * i734.ovli.height * in dispc_errata_i734_wa_init()
4497 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4500 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4502 return -ENOMEM; in dispc_errata_i734_wa_init()
4510 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4513 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4526 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4545 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4563 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4579 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4580 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4581 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4582 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4583 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4604 struct device_node *np = pdev->dev.of_node; in dispc_bind()
4608 return -ENOMEM; in dispc_bind()
4610 dispc->pdev = pdev; in dispc_bind()
4612 dispc->dss = dss; in dispc_bind()
4615 * The OMAP3-based models can't be told apart using the compatible in dispc_bind()
4620 dispc->feat = soc->data; in dispc_bind()
4622 dispc->feat = device_get_match_data(&pdev->dev); in dispc_bind()
4628 dispc->base = devm_platform_ioremap_resource(pdev, 0); in dispc_bind()
4629 if (IS_ERR(dispc->base)) { in dispc_bind()
4630 r = PTR_ERR(dispc->base); in dispc_bind()
4634 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4635 if (dispc->irq < 0) { in dispc_bind()
4637 r = -ENODEV; in dispc_bind()
4641 if (np && of_property_read_bool(np, "syscon-pol")) { in dispc_bind()
4642 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4643 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4644 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); in dispc_bind()
4645 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4649 if (of_property_read_u32_index(np, "syscon-pol", 1, in dispc_bind()
4650 &dispc->syscon_pol_offset)) { in dispc_bind()
4651 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); in dispc_bind()
4652 r = -EINVAL; in dispc_bind()
4661 pm_runtime_enable(&pdev->dev); in dispc_bind()
4670 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
4675 dss->dispc = dispc; in dispc_bind()
4677 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4683 pm_runtime_disable(&pdev->dev); in dispc_bind()
4692 struct dss_device *dss = dispc->dss; in dispc_unbind()
4694 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4696 dss->dispc = NULL; in dispc_unbind()
4712 return component_add(&pdev->dev, &dispc_component_ops); in dispc_probe()
4717 component_del(&pdev->dev, &dispc_component_ops); in dispc_remove()
4724 dispc->is_enabled = false; in dispc_runtime_suspend()
4728 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4755 dispc->is_enabled = true; in dispc_runtime_resume()