35 	while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {  in nv50_gpio_reset()
36 		static const u32 regs[] = { 0xe100, 0xe28c };  in nv50_gpio_reset()
38 		u8  line =   (data & 0x0000001f);  in nv50_gpio_reset()
39 		u8  func =   (data & 0x0000ff00) >> 8;  in nv50_gpio_reset()
40 		u8  defs = !!(data & 0x01000000);  in nv50_gpio_reset()
41 		u8  unk0 = !!(data & 0x02000000);  in nv50_gpio_reset()
42 		u8  unk1 = !!(data & 0x04000000);  in nv50_gpio_reset()
45 		u32 lsh = line & 0x0f;  in nv50_gpio_reset()
51 		nvkm_gpio_set(gpio, 0, func, line, defs);  in nv50_gpio_reset()
53 		nvkm_mask(device, reg, 0x00010001 << lsh, val << lsh);  in nv50_gpio_reset()
60 	const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };  in nv50_gpio_location()
67 	return 0;  in nv50_gpio_location()
80 	return 0;  in nv50_gpio_drive()
99 	u32 intr = nvkm_rd32(device, 0x00e054);  in nv50_gpio_intr_stat()
100 	u32 stat = nvkm_rd32(device, 0x00e050) & intr;  in nv50_gpio_intr_stat()
101 	*lo = (stat & 0xffff0000) >> 16;  in nv50_gpio_intr_stat()
102 	*hi = (stat & 0x0000ffff);  in nv50_gpio_intr_stat()
103 	nvkm_wr32(device, 0x00e054, intr);  in nv50_gpio_intr_stat()
110 	u32 inte = nvkm_rd32(device, 0x00e050);  in nv50_gpio_intr_mask()
115 	nvkm_wr32(device, 0x00e050, inte);  in nv50_gpio_intr_mask()