40 	u32 patt = 0xdeadbeef;  in nv04_devinit_meminit()
52 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);  in nv04_devinit_meminit()
53 	nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);  in nv04_devinit_meminit()
55 	nvkm_mask(device, NV04_PFB_BOOT_0, ~0,  in nv04_devinit_meminit()
60 	for (i = 0; i < 4; i++)  in nv04_devinit_meminit()
63 	fbmem_poke(fb, 0x400000, patt + 1);  in nv04_devinit_meminit()
65 	if (fbmem_peek(fb, 0) == patt + 1) {  in nv04_devinit_meminit()
70 			      NV04_PFB_DEBUG_0_REFRESH_OFF, 0);  in nv04_devinit_meminit()
72 		for (i = 0; i < 4; i++)  in nv04_devinit_meminit()
75 		if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))  in nv04_devinit_meminit()
81 	if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {  in nv04_devinit_meminit()
87 	if (fbmem_peek(fb, 0) != patt) {  in nv04_devinit_meminit()
88 		if (fbmem_readback(fb, 0x800000, patt))  in nv04_devinit_meminit()
100 	if (!fbmem_readback(fb, 0x800000, patt)) {  in nv04_devinit_meminit()
107 	nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);  in nv04_devinit_meminit()
108 	nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);  in nv04_devinit_meminit()
117 	if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)  in powerctrl_1_shift()
121 	case 0x680520:  in powerctrl_1_shift()
123 	case 0x680508:  in powerctrl_1_shift()
125 	case 0x680504:  in powerctrl_1_shift()
127 	case 0x680500:  in powerctrl_1_shift()
135 	if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||  in powerctrl_1_shift()
136 			  chip_version == 0x36 || chip_version >= 0x40))  in powerctrl_1_shift()
149 	int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;  in setPLL_single()
150 	uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;  in setPLL_single()
151 	uint32_t saved_powerctrl_1 = 0;  in setPLL_single()
157 	if (shift_powerctrl_1 >= 0) {  in setPLL_single()
158 		saved_powerctrl_1 = nvkm_rd32(device, 0x001584);  in setPLL_single()
159 		nvkm_wr32(device, 0x001584,  in setPLL_single()
160 			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |  in setPLL_single()
166 		nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff));  in setPLL_single()
169 		nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1);  in setPLL_single()
171 	if ((chip_version < 0x17 || chip_version == 0x1a) &&  in setPLL_single()
172 	    chip_version != 0x11)  in setPLL_single()
180 	if (shift_powerctrl_1 >= 0)  in setPLL_single()
181 		nvkm_wr32(device, 0x001584, saved_powerctrl_1);  in setPLL_single()
187 	bool head_a = (reg1 == 0x680508);  in new_ramdac580()
190 		ramdac580 |= head_a ? 0x00000100 : 0x10000000;  in new_ramdac580()
192 		ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;  in new_ramdac580()
203 	bool nv3035 = chip_version == 0x30 || chip_version == 0x35;  in setPLL_double_highregs()
204 	uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);  in setPLL_double_highregs()
206 	uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;  in setPLL_double_highregs()
207 	uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;  in setPLL_double_highregs()
208 	uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;  in setPLL_double_highregs()
209 	uint32_t oldramdac580 = 0, ramdac580 = 0;  in setPLL_double_highregs()
211 	uint32_t saved_powerctrl_1 = 0, savedc040 = 0;  in setPLL_double_highregs()
216 		pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |  in setPLL_double_highregs()
217 		       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;  in setPLL_double_highregs()
218 		pll2 = 0;  in setPLL_double_highregs()
220 	if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */  in setPLL_double_highregs()
221 		oldramdac580 = nvkm_rd32(device, 0x680580);  in setPLL_double_highregs()
224 			oldpll1 = ~0;	/* force mismatch */  in setPLL_double_highregs()
227 			pll2 |= 0x011f;  in setPLL_double_highregs()
229 	if (chip_version > 0x70)  in setPLL_double_highregs()
231 		pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;  in setPLL_double_highregs()
236 	if (shift_powerctrl_1 >= 0) {  in setPLL_double_highregs()
237 		saved_powerctrl_1 = nvkm_rd32(device, 0x001584);  in setPLL_double_highregs()
238 		nvkm_wr32(device, 0x001584,  in setPLL_double_highregs()
239 			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |  in setPLL_double_highregs()
243 	if (chip_version >= 0x40) {  in setPLL_double_highregs()
247 		case 0x680504:  in setPLL_double_highregs()
249 		case 0x680500:  in setPLL_double_highregs()
251 		case 0x680520:  in setPLL_double_highregs()
253 		case 0x680508:  in setPLL_double_highregs()
257 		savedc040 = nvkm_rd32(device, 0xc040);  in setPLL_double_highregs()
259 			nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040));  in setPLL_double_highregs()
263 		nvkm_wr32(device, 0x680580, ramdac580);  in setPLL_double_highregs()
269 	if (shift_powerctrl_1 >= 0)  in setPLL_double_highregs()
270 		nvkm_wr32(device, 0x001584, saved_powerctrl_1);  in setPLL_double_highregs()
271 	if (chip_version >= 0x40)  in setPLL_double_highregs()
272 		nvkm_wr32(device, 0xc040, savedc040);  in setPLL_double_highregs()
288 	bool mpll = Preg == 0x4020;  in setPLL_double_lowregs()
291 	uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |  in setPLL_double_lowregs()
292 			0xc << 28 | pv->log2P << 16;  in setPLL_double_lowregs()
293 	uint32_t saved4600 = 0;  in setPLL_double_lowregs()
298 	if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)  in setPLL_double_lowregs()
301 	if (Preg == 0x4000)  in setPLL_double_lowregs()
302 		maskc040 = ~0x333;  in setPLL_double_lowregs()
303 	if (Preg == 0x4058)  in setPLL_double_lowregs()
304 		maskc040 = ~(0xc << 24);  in setPLL_double_lowregs()
318 		saved4600 = nvkm_rd32(device, 0x4600);  in setPLL_double_lowregs()
319 		nvkm_wr32(device, 0x4600, saved4600 | 8 << 28);  in setPLL_double_lowregs()
328 		nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28));  in setPLL_double_lowregs()
329 		nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28));  in setPLL_double_lowregs()
332 	savedc040 = nvkm_rd32(device, 0xc040);  in setPLL_double_lowregs()
333 	nvkm_wr32(device, 0xc040, savedc040 & maskc040);  in setPLL_double_lowregs()
336 	if (NMNMreg == 0x4024)  in setPLL_double_lowregs()
337 		nvkm_wr32(device, 0x403c, NMNM);  in setPLL_double_lowregs()
342 		nvkm_wr32(device, 0x4020, Pval);  in setPLL_double_lowregs()
343 		nvkm_wr32(device, 0x4038, Pval);  in setPLL_double_lowregs()
344 		nvkm_wr32(device, 0x4600, saved4600);  in setPLL_double_lowregs()
347 	nvkm_wr32(device, 0xc040, savedc040);  in setPLL_double_lowregs()
350 		nvkm_wr32(device, 0x4020, Pval & ~(1 << 28));  in setPLL_double_lowregs()
351 		nvkm_wr32(device, 0x4038, Pval & ~(1 << 28));  in setPLL_double_lowregs()
366 	ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);  in nv04_devinit_pll_set()
381 	if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||  in nv04_devinit_pll_set()
382 	    cv >= 0x40) {  in nv04_devinit_pll_set()
383 		if (type > 0x405c)  in nv04_devinit_pll_set()
390 	return 0;  in nv04_devinit_pll_set()
407 	nvkm_mask(device, 0x000200, 0x00000001, 0x00000001);  in nv04_devinit_preinit()
410 	if (init->owner < 0)  in nv04_devinit_preinit()
412 	nvkm_wrvgaowner(device, 0);  in nv04_devinit_preinit()
415 		u32 htotal = nvkm_rdvgac(device, 0, 0x06);  in nv04_devinit_preinit()
416 		htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8;  in nv04_devinit_preinit()
417 		htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4;  in nv04_devinit_preinit()
418 		htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10;  in nv04_devinit_preinit()
419 		htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11;  in nv04_devinit_preinit()
448 	return 0;  in nv04_devinit_new_()