Lines Matching +full:0 +full:x0000002d
35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
48 if (ret == 0) { in nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x00, object->oclass); in nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); in nv50_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); in nv50_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); in nv50_gr_object_bind()
75 if (ret == 0) { in nv50_gr_chan_bind()
100 return 0; in nv50_gr_chan_new()
108 { 0x01, "STACK_UNDERFLOW" },
109 { 0x02, "STACK_MISMATCH" },
110 { 0x04, "QUADON_ACTIVE" },
111 { 0x08, "TIMEOUT" },
112 { 0x10, "INVALID_OPCODE" },
113 { 0x20, "PM_OVERFLOW" },
114 { 0x40, "BREAKPOINT" },
119 { 0x0000001, "LOCAL_LIMIT_READ" },
120 { 0x0000010, "LOCAL_LIMIT_WRITE" },
121 { 0x0000040, "STACK_LIMIT" },
122 { 0x0000100, "GLOBAL_LIMIT_READ" },
123 { 0x0001000, "GLOBAL_LIMIT_WRITE" },
124 { 0x0010000, "MP0" },
125 { 0x0020000, "MP1" },
126 { 0x0040000, "GLOBAL_LIMIT_RED" },
127 { 0x0400000, "GLOBAL_LIMIT_ATOM" },
128 { 0x4000000, "MP2" },
133 { 0x00000001, "" }, /* any bit set? */
134 { 0x00000002, "FAULT" },
135 { 0x00000004, "STORAGE_TYPE_MISMATCH" },
136 { 0x00000008, "LINEAR_MISMATCH" },
137 { 0x00000020, "WRONG_MEMTYPE" },
142 { 0x00000001, "NOTIFY" },
143 { 0x00000002, "IN" },
144 { 0x00000004, "OUT" },
149 { 0x00000001, "FAULT" },
154 { 0x00000001, "FAULT" },
159 { 0x00000001, "FAULT" },
165 { 0x00000003, "INVALID_OPERATION", NULL },
166 { 0x00000004, "INVALID_VALUE", NULL },
167 { 0x00000005, "INVALID_ENUM", NULL },
168 { 0x00000008, "INVALID_OBJECT", NULL },
169 { 0x00000009, "READ_ONLY_OBJECT", NULL },
170 { 0x0000000a, "SUPERVISOR_OBJECT", NULL },
171 { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL },
172 { 0x0000000c, "INVALID_BITFIELD", NULL },
173 { 0x0000000d, "BEGIN_END_ACTIVE", NULL },
174 { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL },
175 { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL },
176 { 0x00000010, "RT_DOUBLE_BIND", NULL },
177 { 0x00000011, "RT_TYPES_MISMATCH", NULL },
178 { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL },
179 { 0x00000015, "FP_TOO_FEW_REGS", NULL },
180 { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL },
181 { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL },
182 { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL },
183 { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL },
184 { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL },
185 { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL },
186 { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL },
187 { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL },
188 { 0x0000001f, "RT_BPP128_WITH_MS8", NULL },
189 { 0x00000021, "Z_OUT_OF_BOUNDS", NULL },
190 { 0x00000023, "XY_OUT_OF_BOUNDS", NULL },
191 { 0x00000024, "VP_ZERO_INPUTS", NULL },
192 { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL },
193 { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL },
194 { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL },
195 { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL },
196 { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL },
197 { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL },
198 { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL },
199 { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL },
200 { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL },
201 { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL },
202 { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL },
203 { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL },
204 { 0x00000046, "LAYER_ID_NEEDS_GP", NULL },
205 { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL },
206 { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL },
211 { 0x00000001, "NOTIFY" },
212 { 0x00000002, "COMPUTE_QUERY" },
213 { 0x00000010, "ILLEGAL_MTHD" },
214 { 0x00000020, "ILLEGAL_CLASS" },
215 { 0x00000040, "DOUBLE_NOTIFY" },
216 { 0x00001000, "CONTEXT_SWITCH" },
217 { 0x00010000, "BUFFER_NOTIFY" },
218 { 0x00100000, "DATA_ERROR" },
219 { 0x00200000, "TRAP" },
220 { 0x01000000, "SINGLE_STEP" },
225 { 0x00000004, "SURF_WIDTH_OVERRUN" },
226 { 0x00000008, "SURF_HEIGHT_OVERRUN" },
227 { 0x00000010, "DST2D_FAULT" },
228 { 0x00000020, "ZETA_FAULT" },
229 { 0x00000040, "RT_FAULT" },
230 { 0x00000080, "CUDA_FAULT" },
231 { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" },
232 { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" },
233 { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" },
234 { 0x00000800, "DST2D_LINEAR_MISMATCH" },
235 { 0x00001000, "RT_LINEAR_MISMATCH" },
244 u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04); in nv50_gr_prop_trap()
245 u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08); in nv50_gr_prop_trap()
246 u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c); in nv50_gr_prop_trap()
247 u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10); in nv50_gr_prop_trap()
248 u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14); in nv50_gr_prop_trap()
249 u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18); in nv50_gr_prop_trap()
250 u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c); in nv50_gr_prop_trap()
254 if (ustatus & 0x00000080) { in nv50_gr_prop_trap()
255 if (e18 & 0x80000000) { in nv50_gr_prop_trap()
258 tp, e14, e10 | ((e18 >> 24) & 0x1f)); in nv50_gr_prop_trap()
259 e18 &= ~0x1f000000; in nv50_gr_prop_trap()
260 } else if (e18 & 0xc) { in nv50_gr_prop_trap()
263 tp, e14, e10 | ((e18 >> 7) & 0x1f)); in nv50_gr_prop_trap()
264 e18 &= ~0x00000f80; in nv50_gr_prop_trap()
269 ustatus &= ~0x00000080; in nv50_gr_prop_trap()
286 u32 units = nvkm_rd32(device, 0x1540); in nv50_gr_mp_trap()
290 int mps = 0; in nv50_gr_mp_trap()
291 for (i = 0; i < 4; i++) { in nv50_gr_mp_trap()
294 if (device->chipset < 0xa0) in nv50_gr_mp_trap()
295 addr = 0x408200 + (tpid << 12) + (i << 7); in nv50_gr_mp_trap()
297 addr = 0x408100 + (tpid << 11) + (i << 7); in nv50_gr_mp_trap()
298 mp10 = nvkm_rd32(device, addr + 0x10); in nv50_gr_mp_trap()
299 status = nvkm_rd32(device, addr + 0x14); in nv50_gr_mp_trap()
303 nvkm_rd32(device, addr + 0x20); in nv50_gr_mp_trap()
304 pc = nvkm_rd32(device, addr + 0x24); in nv50_gr_mp_trap()
305 oplow = nvkm_rd32(device, addr + 0x70); in nv50_gr_mp_trap()
306 ophigh = nvkm_rd32(device, addr + 0x74); in nv50_gr_mp_trap()
312 tpid, i, status, msg, pc & 0xffffff, in nv50_gr_mp_trap()
315 nvkm_wr32(device, addr + 0x10, mp10); in nv50_gr_mp_trap()
316 nvkm_wr32(device, addr + 0x14, 0); in nv50_gr_mp_trap()
330 u32 units = nvkm_rd32(device, 0x1540); in nv50_gr_tp_trap()
331 int tps = 0; in nv50_gr_tp_trap()
335 for (i = 0; i < 16; i++) { in nv50_gr_tp_trap()
338 if (device->chipset < 0xa0) in nv50_gr_tp_trap()
342 ustatus = nvkm_rd32(device, ustatus_addr) & 0x7fffffff; in nv50_gr_tp_trap()
350 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) in nv50_gr_tp_trap()
359 ustatus = 0; in nv50_gr_tp_trap()
364 if (ustatus & 0x04030000) { in nv50_gr_tp_trap()
366 ustatus &= ~0x04030000; in nv50_gr_tp_trap()
373 ustatus = 0; in nv50_gr_tp_trap()
380 ustatus = 0; in nv50_gr_tp_trap()
387 nvkm_wr32(device, ustatus_addr, 0xc0000000); in nv50_gr_tp_trap()
400 u32 status = nvkm_rd32(device, 0x400108); in nv50_gr_trap_handler()
412 if (status & 0x001) { in nv50_gr_trap_handler()
413 ustatus = nvkm_rd32(device, 0x400804) & 0x7fffffff; in nv50_gr_trap_handler()
418 nvkm_wr32(device, 0x400500, 0x00000000); in nv50_gr_trap_handler()
421 if (ustatus & 0x00000001) { in nv50_gr_trap_handler()
422 u32 addr = nvkm_rd32(device, 0x400808); in nv50_gr_trap_handler()
423 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_trap_handler()
424 u32 mthd = (addr & 0x00001ffc); in nv50_gr_trap_handler()
425 u32 datal = nvkm_rd32(device, 0x40080c); in nv50_gr_trap_handler()
426 u32 datah = nvkm_rd32(device, 0x400810); in nv50_gr_trap_handler()
427 u32 class = nvkm_rd32(device, 0x400814); in nv50_gr_trap_handler()
428 u32 r848 = nvkm_rd32(device, 0x400848); in nv50_gr_trap_handler()
431 if (display && (addr & 0x80000000)) { in nv50_gr_trap_handler()
443 nvkm_wr32(device, 0x400808, 0); in nv50_gr_trap_handler()
444 nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); in nv50_gr_trap_handler()
445 nvkm_wr32(device, 0x400848, 0); in nv50_gr_trap_handler()
446 ustatus &= ~0x00000001; in nv50_gr_trap_handler()
449 if (ustatus & 0x00000002) { in nv50_gr_trap_handler()
450 u32 addr = nvkm_rd32(device, 0x40084c); in nv50_gr_trap_handler()
451 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_trap_handler()
452 u32 mthd = (addr & 0x00001ffc); in nv50_gr_trap_handler()
453 u32 data = nvkm_rd32(device, 0x40085c); in nv50_gr_trap_handler()
454 u32 class = nvkm_rd32(device, 0x400814); in nv50_gr_trap_handler()
457 if (display && (addr & 0x80000000)) { in nv50_gr_trap_handler()
468 nvkm_wr32(device, 0x40084c, 0); in nv50_gr_trap_handler()
469 ustatus &= ~0x00000002; in nv50_gr_trap_handler()
477 nvkm_wr32(device, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
478 nvkm_wr32(device, 0x400108, 0x001); in nv50_gr_trap_handler()
479 status &= ~0x001; in nv50_gr_trap_handler()
481 return 0; in nv50_gr_trap_handler()
485 if (status & 0x002) { in nv50_gr_trap_handler()
486 u32 ustatus = nvkm_rd32(device, 0x406800) & 0x7fffffff; in nv50_gr_trap_handler()
493 nvkm_rd32(device, 0x406804), in nv50_gr_trap_handler()
494 nvkm_rd32(device, 0x406808), in nv50_gr_trap_handler()
495 nvkm_rd32(device, 0x40680c), in nv50_gr_trap_handler()
496 nvkm_rd32(device, 0x406810)); in nv50_gr_trap_handler()
500 nvkm_wr32(device, 0x400040, 2); in nv50_gr_trap_handler()
501 nvkm_wr32(device, 0x400040, 0); in nv50_gr_trap_handler()
502 nvkm_wr32(device, 0x406800, 0xc0000000); in nv50_gr_trap_handler()
503 nvkm_wr32(device, 0x400108, 0x002); in nv50_gr_trap_handler()
504 status &= ~0x002; in nv50_gr_trap_handler()
508 if (status & 0x004) { in nv50_gr_trap_handler()
509 u32 ustatus = nvkm_rd32(device, 0x400c04) & 0x7fffffff; in nv50_gr_trap_handler()
516 nvkm_rd32(device, 0x400c00), in nv50_gr_trap_handler()
517 nvkm_rd32(device, 0x400c08), in nv50_gr_trap_handler()
518 nvkm_rd32(device, 0x400c0c), in nv50_gr_trap_handler()
519 nvkm_rd32(device, 0x400c10)); in nv50_gr_trap_handler()
522 nvkm_wr32(device, 0x400c04, 0xc0000000); in nv50_gr_trap_handler()
523 nvkm_wr32(device, 0x400108, 0x004); in nv50_gr_trap_handler()
524 status &= ~0x004; in nv50_gr_trap_handler()
528 if (status & 0x008) { in nv50_gr_trap_handler()
529 ustatus = nvkm_rd32(device, 0x401800) & 0x7fffffff; in nv50_gr_trap_handler()
536 nvkm_rd32(device, 0x401804), in nv50_gr_trap_handler()
537 nvkm_rd32(device, 0x401808), in nv50_gr_trap_handler()
538 nvkm_rd32(device, 0x40180c), in nv50_gr_trap_handler()
539 nvkm_rd32(device, 0x401810)); in nv50_gr_trap_handler()
543 nvkm_wr32(device, 0x400040, 0x80); in nv50_gr_trap_handler()
544 nvkm_wr32(device, 0x400040, 0); in nv50_gr_trap_handler()
545 nvkm_wr32(device, 0x401800, 0xc0000000); in nv50_gr_trap_handler()
546 nvkm_wr32(device, 0x400108, 0x008); in nv50_gr_trap_handler()
547 status &= ~0x008; in nv50_gr_trap_handler()
551 if (status & 0x010) { in nv50_gr_trap_handler()
552 ustatus = nvkm_rd32(device, 0x405018) & 0x7fffffff; in nv50_gr_trap_handler()
560 nvkm_rd32(device, 0x405000), in nv50_gr_trap_handler()
561 nvkm_rd32(device, 0x405004), in nv50_gr_trap_handler()
562 nvkm_rd32(device, 0x405008), in nv50_gr_trap_handler()
563 nvkm_rd32(device, 0x40500c), in nv50_gr_trap_handler()
564 nvkm_rd32(device, 0x405010), in nv50_gr_trap_handler()
565 nvkm_rd32(device, 0x405014), in nv50_gr_trap_handler()
566 nvkm_rd32(device, 0x40501c)); in nv50_gr_trap_handler()
569 nvkm_wr32(device, 0x405018, 0xc0000000); in nv50_gr_trap_handler()
570 nvkm_wr32(device, 0x400108, 0x010); in nv50_gr_trap_handler()
571 status &= ~0x010; in nv50_gr_trap_handler()
574 /* Unknown, not seen yet... 0x402000 is the only trap status reg in nv50_gr_trap_handler()
577 if (status & 0x20) { in nv50_gr_trap_handler()
578 ustatus = nvkm_rd32(device, 0x402000) & 0x7fffffff; in nv50_gr_trap_handler()
581 nvkm_wr32(device, 0x402000, 0xc0000000); in nv50_gr_trap_handler()
586 if (status & 0x040) { in nv50_gr_trap_handler()
587 nv50_gr_tp_trap(gr, 6, 0x408900, 0x408600, display, in nv50_gr_trap_handler()
589 nvkm_wr32(device, 0x400108, 0x040); in nv50_gr_trap_handler()
590 status &= ~0x040; in nv50_gr_trap_handler()
594 if (status & 0x080) { in nv50_gr_trap_handler()
595 nv50_gr_tp_trap(gr, 7, 0x408314, 0x40831c, display, in nv50_gr_trap_handler()
597 nvkm_wr32(device, 0x400108, 0x080); in nv50_gr_trap_handler()
598 status &= ~0x080; in nv50_gr_trap_handler()
603 if (status & 0x100) { in nv50_gr_trap_handler()
604 nv50_gr_tp_trap(gr, 8, 0x408e08, 0x408708, display, in nv50_gr_trap_handler()
606 nvkm_wr32(device, 0x400108, 0x100); in nv50_gr_trap_handler()
607 status &= ~0x100; in nv50_gr_trap_handler()
613 nvkm_wr32(device, 0x400108, status); in nv50_gr_trap_handler()
626 u32 stat = nvkm_rd32(device, 0x400100); in nv50_gr_intr()
627 u32 inst = nvkm_rd32(device, 0x40032c) & 0x0fffffff; in nv50_gr_intr()
628 u32 addr = nvkm_rd32(device, 0x400704); in nv50_gr_intr()
629 u32 subc = (addr & 0x00070000) >> 16; in nv50_gr_intr()
630 u32 mthd = (addr & 0x00001ffc); in nv50_gr_intr()
631 u32 data = nvkm_rd32(device, 0x400708); in nv50_gr_intr()
632 u32 class = nvkm_rd32(device, 0x400814); in nv50_gr_intr()
646 if (show & 0x00100000) { in nv50_gr_intr()
647 u32 ecode = nvkm_rd32(device, 0x400110); in nv50_gr_intr()
651 show_bitfield &= ~0x00100000; in nv50_gr_intr()
654 if (stat & 0x00200000) { in nv50_gr_intr()
656 show &= ~0x00200000; in nv50_gr_intr()
657 show_bitfield &= ~0x00200000; in nv50_gr_intr()
660 nvkm_wr32(device, 0x400100, stat); in nv50_gr_intr()
661 nvkm_wr32(device, 0x400500, 0x00010001); in nv50_gr_intr()
672 if (nvkm_rd32(device, 0x400824) & (1 << 31)) in nv50_gr_intr()
673 nvkm_wr32(device, 0x400824, nvkm_rd32(device, 0x400824) & ~(1 << 31)); in nv50_gr_intr()
686 nvkm_wr32(device, 0x40008c, 0x00000004); in nv50_gr_init()
689 nvkm_wr32(device, 0x400804, 0xc0000000); in nv50_gr_init()
690 nvkm_wr32(device, 0x406800, 0xc0000000); in nv50_gr_init()
691 nvkm_wr32(device, 0x400c04, 0xc0000000); in nv50_gr_init()
692 nvkm_wr32(device, 0x401800, 0xc0000000); in nv50_gr_init()
693 nvkm_wr32(device, 0x405018, 0xc0000000); in nv50_gr_init()
694 nvkm_wr32(device, 0x402000, 0xc0000000); in nv50_gr_init()
696 units = nvkm_rd32(device, 0x001540); in nv50_gr_init()
697 for (i = 0; i < 16; i++) { in nv50_gr_init()
701 if (device->chipset < 0xa0) { in nv50_gr_init()
702 nvkm_wr32(device, 0x408900 + (i << 12), 0xc0000000); in nv50_gr_init()
703 nvkm_wr32(device, 0x408e08 + (i << 12), 0xc0000000); in nv50_gr_init()
704 nvkm_wr32(device, 0x408314 + (i << 12), 0xc0000000); in nv50_gr_init()
706 nvkm_wr32(device, 0x408600 + (i << 11), 0xc0000000); in nv50_gr_init()
707 nvkm_wr32(device, 0x408708 + (i << 11), 0xc0000000); in nv50_gr_init()
708 nvkm_wr32(device, 0x40831c + (i << 11), 0xc0000000); in nv50_gr_init()
712 nvkm_wr32(device, 0x400108, 0xffffffff); in nv50_gr_init()
713 nvkm_wr32(device, 0x400138, 0xffffffff); in nv50_gr_init()
714 nvkm_wr32(device, 0x400100, 0xffffffff); in nv50_gr_init()
715 nvkm_wr32(device, 0x40013c, 0xffffffff); in nv50_gr_init()
716 nvkm_wr32(device, 0x400500, 0x00010001); in nv50_gr_init()
723 nvkm_wr32(device, 0x400824, 0x00000000); in nv50_gr_init()
724 nvkm_wr32(device, 0x400828, 0x00000000); in nv50_gr_init()
725 nvkm_wr32(device, 0x40082c, 0x00000000); in nv50_gr_init()
726 nvkm_wr32(device, 0x400830, 0x00000000); in nv50_gr_init()
727 nvkm_wr32(device, 0x40032c, 0x00000000); in nv50_gr_init()
728 nvkm_wr32(device, 0x400330, 0x00000000); in nv50_gr_init()
731 switch (device->chipset & 0xf0) { in nv50_gr_init()
732 case 0x50: in nv50_gr_init()
733 case 0x80: in nv50_gr_init()
734 case 0x90: in nv50_gr_init()
735 nvkm_wr32(device, 0x402ca8, 0x00000800); in nv50_gr_init()
737 case 0xa0: in nv50_gr_init()
739 if (device->chipset == 0xa0 || in nv50_gr_init()
740 device->chipset == 0xaa || in nv50_gr_init()
741 device->chipset == 0xac) { in nv50_gr_init()
742 nvkm_wr32(device, 0x402ca8, 0x00000802); in nv50_gr_init()
744 nvkm_wr32(device, 0x402cc0, 0x00000000); in nv50_gr_init()
745 nvkm_wr32(device, 0x402ca8, 0x00000002); in nv50_gr_init()
752 for (i = 0; i < 8; i++) { in nv50_gr_init()
753 nvkm_wr32(device, 0x402c20 + (i * 0x10), 0x00000000); in nv50_gr_init()
754 nvkm_wr32(device, 0x402c24 + (i * 0x10), 0x00000000); in nv50_gr_init()
755 nvkm_wr32(device, 0x402c28 + (i * 0x10), 0x00000000); in nv50_gr_init()
756 nvkm_wr32(device, 0x402c2c + (i * 0x10), 0x00000000); in nv50_gr_init()
759 return 0; in nv50_gr_init()