Lines Matching full:device
36 return nvkm_rd32(gr->engine.subdev.device, 0x1540);
47 int ret = nvkm_gpuobj_new(object->engine->subdev.device, 20, align,
79 int ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
97 struct nvkm_device *device = subdev->device;
101 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
103 if (nvkm_rd32(device, 0x40032c) == inst) {
105 nvkm_wr32(device, 0x400720, 0x00000000);
106 nvkm_wr32(device, 0x400784, inst);
107 nvkm_mask(device, 0x400310, 0x00000020, 0x00000020);
108 nvkm_mask(device, 0x400304, 0x00000001, 0x00000001);
109 if (nvkm_msec(device, 2000,
110 if (!(nvkm_rd32(device, 0x400300) & 0x00000001))
113 u32 insn = nvkm_rd32(device, 0x400308);
119 nvkm_mask(device, 0x40032c, 0x01000000, 0x00000000);
122 if (nvkm_rd32(device, 0x400330) == inst)
123 nvkm_mask(device, 0x400330, 0x01000000, 0x00000000);
125 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
176 struct nvkm_device *device = gr->base.engine.subdev.device;
177 struct nvkm_fifo *fifo = device->fifo;
183 switch (device->chipset) {
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
195 switch (device->chipset) {
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp);
204 nvkm_wr32(device, NV41_PGRAPH_ZCOMP0(i), tile->zcomp);
205 nvkm_wr32(device, NV41_PGRAPH_ZCOMP1(i), tile->zcomp);
214 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
215 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
216 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
217 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
218 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
219 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
220 nvkm_wr32(device, NV47_PGRAPH_ZCOMP0(i), tile->zcomp);
221 nvkm_wr32(device, NV47_PGRAPH_ZCOMP1(i), tile->zcomp);
237 struct nvkm_device *device = subdev->device;
238 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
239 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
240 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
241 u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff;
242 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
245 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
246 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xffff;
263 nvkm_mask(device, 0x402000, 0, 0);
267 nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
268 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
290 struct nvkm_device *device = gr->base.engine.subdev.device;
295 ret = nv40_grctx_init(device, &gr->size);
300 nvkm_wr32(device, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
302 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
303 nvkm_wr32(device, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
305 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
306 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
307 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0);
308 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
309 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000);
310 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
312 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
313 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
315 j = nvkm_rd32(device, 0x1540) & 0xff;
319 nvkm_wr32(device, 0x405000, i);
322 if (device->chipset == 0x40) {
323 nvkm_wr32(device, 0x4009b0, 0x83280fff);
324 nvkm_wr32(device, 0x4009b4, 0x000000a0);
326 nvkm_wr32(device, 0x400820, 0x83280eff);
327 nvkm_wr32(device, 0x400824, 0x000000a0);
330 switch (device->chipset) {
333 nvkm_wr32(device, 0x4009b8, 0x0078e366);
334 nvkm_wr32(device, 0x4009bc, 0x0000014c);
339 nvkm_wr32(device, 0x400828, 0x007596ff);
340 nvkm_wr32(device, 0x40082c, 0x00000108);
343 nvkm_wr32(device, 0x400828, 0x0072cb77);
344 nvkm_wr32(device, 0x40082c, 0x00000108);
351 nvkm_wr32(device, 0x400860, 0);
352 nvkm_wr32(device, 0x400864, 0);
357 nvkm_wr32(device, 0x400828, 0x07830610);
358 nvkm_wr32(device, 0x40082c, 0x0000016A);
364 nvkm_wr32(device, 0x400b38, 0x2ffff800);
365 nvkm_wr32(device, 0x400b3c, 0x00006000);
368 switch (device->chipset) {
371 nvkm_wr32(device, 0x400bc4, 0x1003d888);
372 nvkm_wr32(device, 0x400bbc, 0xb7a7b500);
375 nvkm_wr32(device, 0x400bc4, 0x0000e024);
376 nvkm_wr32(device, 0x400bbc, 0xb7a7b520);
381 nvkm_wr32(device, 0x400bc4, 0x1003d888);
382 nvkm_wr32(device, 0x400bbc, 0xb7a7b540);
389 vramsz = device->func->resource_size(device, NVKM_BAR1_FB) - 1;
390 switch (device->chipset) {
392 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
393 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
394 nvkm_wr32(device, 0x4069A4, nvkm_rd32(device, 0x100200));
395 nvkm_wr32(device, 0x4069A8, nvkm_rd32(device, 0x100204));
396 nvkm_wr32(device, 0x400820, 0);
397 nvkm_wr32(device, 0x400824, 0);
398 nvkm_wr32(device, 0x400864, vramsz);
399 nvkm_wr32(device, 0x400868, vramsz);
402 switch (device->chipset) {
410 nvkm_wr32(device, 0x4009F0, nvkm_rd32(device, 0x100200));
411 nvkm_wr32(device, 0x4009F4, nvkm_rd32(device, 0x100204));
414 nvkm_wr32(device, 0x400DF0, nvkm_rd32(device, 0x100200));
415 nvkm_wr32(device, 0x400DF4, nvkm_rd32(device, 0x100204));
418 nvkm_wr32(device, 0x4069F0, nvkm_rd32(device, 0x100200));
419 nvkm_wr32(device, 0x4069F4, nvkm_rd32(device, 0x100204));
420 nvkm_wr32(device, 0x400840, 0);
421 nvkm_wr32(device, 0x400844, 0);
422 nvkm_wr32(device, 0x4008A0, vramsz);
423 nvkm_wr32(device, 0x4008A4, vramsz);
431 nv40_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
441 return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
473 nv40_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
475 return nv40_gr_new_(&nv40_gr, device, type, inst, pgr);