Lines Matching full:device
34 struct nvkm_device *device = gr->base.engine.subdev.device;
38 nvkm_mask(device, 0x400720, 0x00000001, 0x00000000);
39 if (nvkm_rd32(device, 0x400144) & 0x00010000)
40 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24;
42 nvkm_wr32(device, 0x400784, inst >> 4);
43 nvkm_wr32(device, 0x400788, 0x00000002);
44 nvkm_msec(device, 2000,
45 if (!nvkm_rd32(device, 0x400700))
48 nvkm_wr32(device, 0x400144, 0x10000000);
49 nvkm_mask(device, 0x400148, 0xff000000, 0x1f000000);
51 nvkm_mask(device, 0x400720, 0x00000001, 0x00000001);
89 ret = nvkm_memory_new(gr->base.engine.subdev.device,
152 struct nvkm_device *device = gr->base.engine.subdev.device;
153 struct nvkm_fifo *fifo = device->fifo;
159 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
160 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
161 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
163 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i);
164 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit);
165 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i);
166 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch);
167 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i);
168 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->addr);
170 if (device->chipset != 0x34) {
171 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp);
172 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i);
173 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->zcomp);
184 struct nvkm_device *device = subdev->device;
186 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR);
187 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE);
188 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS);
189 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR);
193 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA);
194 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff;
201 nvkm_wr32(device, NV03_PGRAPH_INTR, stat);
202 nvkm_wr32(device, NV04_PGRAPH_FIFO, 0x00000001);
223 return nvkm_memory_new(gr->base.engine.subdev.device,
232 struct nvkm_device *device = gr->base.engine.subdev.device;
236 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE,
239 if (device->chipset == 0x20) {
240 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x003d0000);
242 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
243 nvkm_msec(device, 2000,
244 if (!nvkm_rd32(device, 0x400700))
248 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x02c80000);
250 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, 0x00000000);
251 nvkm_msec(device, 2000,
252 if (!nvkm_rd32(device, 0x400700))
257 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF);
258 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
260 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
261 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000);
262 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x00118700);
263 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */
264 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00000000);
265 nvkm_wr32(device, 0x40009C , 0x00000040);
267 if (device->chipset >= 0x25) {
268 nvkm_wr32(device, 0x400890, 0x00a8cfff);
269 nvkm_wr32(device, 0x400610, 0x304B1FB6);
270 nvkm_wr32(device, 0x400B80, 0x1cbd3883);
271 nvkm_wr32(device, 0x400B84, 0x44000000);
272 nvkm_wr32(device, 0x400098, 0x40000080);
273 nvkm_wr32(device, 0x400B88, 0x000000ff);
276 nvkm_wr32(device, 0x400880, 0x0008c7df);
277 nvkm_wr32(device, 0x400094, 0x00000005);
278 nvkm_wr32(device, 0x400B80, 0x45eae20e);
279 nvkm_wr32(device, 0x400B84, 0x24000000);
280 nvkm_wr32(device, 0x400098, 0x00000040);
281 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E00038);
282 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
283 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00E10038);
284 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , 0x00000030);
287 nvkm_wr32(device, 0x4009a0, nvkm_rd32(device, 0x100324));
288 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA000C);
289 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, nvkm_rd32(device, 0x100324));
291 nvkm_wr32(device, NV10_PGRAPH_CTX_CONTROL, 0x10000100);
292 nvkm_wr32(device, NV10_PGRAPH_STATE , 0xFFFFFFFF);
294 tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) & 0x0007ff00;
295 nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
296 tmp = nvkm_rd32(device, NV10_PGRAPH_SURFACE) | 0x00020100;
297 nvkm_wr32(device, NV10_PGRAPH_SURFACE, tmp);
300 vramsz = device->func->resource_size(device, NVKM_BAR1_FB) - 1;
301 nvkm_wr32(device, 0x4009A4, nvkm_rd32(device, 0x100200));
302 nvkm_wr32(device, 0x4009A8, nvkm_rd32(device, 0x100204));
303 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0000);
304 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100200));
305 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0004);
306 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA , nvkm_rd32(device, 0x100204));
307 nvkm_wr32(device, 0x400820, 0);
308 nvkm_wr32(device, 0x400824, 0);
309 nvkm_wr32(device, 0x400864, vramsz - 1);
310 nvkm_wr32(device, 0x400868, vramsz - 1);
313 nvkm_wr32(device, 0x400B20, 0x00000000);
314 nvkm_wr32(device, 0x400B04, 0xFFFFFFFF);
316 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
317 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
318 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
319 nvkm_wr32(device, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
332 nv20_gr_new_(const struct nvkm_gr_func *func, struct nvkm_device *device,
341 return nvkm_gr_ctor(func, device, type, inst, true, &gr->base);
373 nv20_gr_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_gr **pgr)
375 return nv20_gr_new_(&nv20_gr, device, type, inst, pgr);