38 	const u32 soff = ior->id * 0x800;  in gt215_sor_hda_eld()
41 	for (i = 0; i < size; i++)  in gt215_sor_hda_eld()
42 		nvkm_wr32(device, 0x61c440 + soff, (i << 8) | data[i]);  in gt215_sor_hda_eld()
43 	for (; i < 0x60; i++)  in gt215_sor_hda_eld()
44 		nvkm_wr32(device, 0x61c440 + soff, (i << 8));  in gt215_sor_hda_eld()
45 	nvkm_mask(device, 0x61c448 + soff, 0x80000002, 0x80000002);  in gt215_sor_hda_eld()
52 	u32 data = 0x80000000;  in gt215_sor_hda_hpd()
53 	u32 mask = 0x80000001;  in gt215_sor_hda_hpd()
55 		data |= 0x00000001;  in gt215_sor_hda_hpd()
57 		mask |= 0x00000002;  in gt215_sor_hda_hpd()
58 	nvkm_mask(device, 0x61c448 + ior->id * 0x800, mask, data);  in gt215_sor_hda_hpd()
72 	const u32 data = 0x80000000 | (0x00000001 * enable);  in gt215_sor_dp_audio()
73 	const u32 mask = 0x8000000d;  in gt215_sor_dp_audio()
75 	nvkm_mask(device, 0x61c1e0 + soff, mask, data);  in gt215_sor_dp_audio()
77 		if (!(nvkm_rd32(device, 0x61c1e0 + soff) & 0x80000000))  in gt215_sor_dp_audio()
84 	.lanes = { 2, 1, 0, 3 },
104 	nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010000);  in gt215_sor_hdmi_infoframe_vsi()
108 	nvkm_wr32(device, 0x61c544 + soff, vsi.header);  in gt215_sor_hdmi_infoframe_vsi()
109 	nvkm_wr32(device, 0x61c548 + soff, vsi.subpack0_low);  in gt215_sor_hdmi_infoframe_vsi()
110 	nvkm_wr32(device, 0x61c54c + soff, vsi.subpack0_high);  in gt215_sor_hdmi_infoframe_vsi()
112 	/* nvkm_wr32(device, 0x61c550 + soff, vsi.subpack1_low); */  in gt215_sor_hdmi_infoframe_vsi()
113 	/* nvkm_wr32(device, 0x61c554 + soff, vsi.subpack1_high); */  in gt215_sor_hdmi_infoframe_vsi()
115 	nvkm_mask(device, 0x61c53c + soff, 0x00010001, 0x00010001);  in gt215_sor_hdmi_infoframe_vsi()
127 	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);  in gt215_sor_hdmi_infoframe_avi()
131 	nvkm_wr32(device, 0x61c528 + soff, avi.header);  in gt215_sor_hdmi_infoframe_avi()
132 	nvkm_wr32(device, 0x61c52c + soff, avi.subpack0_low);  in gt215_sor_hdmi_infoframe_avi()
133 	nvkm_wr32(device, 0x61c530 + soff, avi.subpack0_high);  in gt215_sor_hdmi_infoframe_avi()
134 	nvkm_wr32(device, 0x61c534 + soff, avi.subpack1_low);  in gt215_sor_hdmi_infoframe_avi()
135 	nvkm_wr32(device, 0x61c538 + soff, avi.subpack1_high);  in gt215_sor_hdmi_infoframe_avi()
137 	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001);  in gt215_sor_hdmi_infoframe_avi()
144 	const u32 ctrl = 0x40000000 * enable |  in gt215_sor_hdmi_ctrl()
145 			 0x1f000000 /* ??? */ |  in gt215_sor_hdmi_ctrl()
150 	if (!(ctrl & 0x40000000)) {  in gt215_sor_hdmi_ctrl()
151 		nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000);  in gt215_sor_hdmi_ctrl()
152 		nvkm_mask(device, 0x61c53c + soff, 0x00000001, 0x00000000);  in gt215_sor_hdmi_ctrl()
153 		nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);  in gt215_sor_hdmi_ctrl()
154 		nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);  in gt215_sor_hdmi_ctrl()
159 	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);  in gt215_sor_hdmi_ctrl()
160 	nvkm_wr32(device, 0x61c508 + soff, 0x000a0184);  in gt215_sor_hdmi_ctrl()
161 	nvkm_wr32(device, 0x61c50c + soff, 0x00000071);  in gt215_sor_hdmi_ctrl()
162 	nvkm_wr32(device, 0x61c510 + soff, 0x00000000);  in gt215_sor_hdmi_ctrl()
163 	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001);  in gt215_sor_hdmi_ctrl()
165 	nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */  in gt215_sor_hdmi_ctrl()
166 	nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */  in gt215_sor_hdmi_ctrl()
167 	nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */  in gt215_sor_hdmi_ctrl()
170 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */  in gt215_sor_hdmi_ctrl()
171 	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */  in gt215_sor_hdmi_ctrl()
172 	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */  in gt215_sor_hdmi_ctrl()
175 	nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);  in gt215_sor_hdmi_ctrl()
192 	div = nvkm_rd32(device, 0x61c080 + soff);  in gt215_sor_bl_set()
195 		nvkm_wr32(device, 0x61c084 + soff, 0xc0000000 | val);  in gt215_sor_bl_set()
197 	return 0;  in gt215_sor_bl_set()
207 	div  = nvkm_rd32(device, 0x61c080 + soff);  in gt215_sor_bl_get()
208 	val  = nvkm_rd32(device, 0x61c084 + soff);  in gt215_sor_bl_get()
209 	val &= 0x00ffffff;  in gt215_sor_bl_get()
251 	.root = { 0,0,GT214_DISP },
253 		{{0,0,GT214_DISP_CURSOR             }, nvkm_disp_chan_new, & nv50_disp_curs },
254 		{{0,0,GT214_DISP_OVERLAY            }, nvkm_disp_chan_new, & nv50_disp_oimm },
255 		{{0,0,GT214_DISP_BASE_CHANNEL_DMA   }, nvkm_disp_chan_new, &  g84_disp_base },
256 		{{0,0,GT214_DISP_CORE_CHANNEL_DMA   }, nvkm_disp_core_new, &  g94_disp_core },
257 		{{0,0,GT214_DISP_OVERLAY_CHANNEL_DMA}, nvkm_disp_chan_new, &  g84_disp_ovly },