Lines Matching refs:asyh
370 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); in nv50_outp_atomic_fix_depth() local
372 struct drm_display_mode *mode = &asyh->state.adjusted_mode; in nv50_outp_atomic_fix_depth()
380 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10); in nv50_outp_atomic_fix_depth()
383 while (asyh->or.bpc > 6) { in nv50_outp_atomic_fix_depth()
384 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8); in nv50_outp_atomic_fix_depth()
388 asyh->or.bpc -= 2; in nv50_outp_atomic_fix_depth()
403 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); in nv50_outp_atomic_check() local
412 asyh->or.bpc = connector->display_info.bpc; in nv50_outp_atomic_check()
487 struct nv50_head_atom *asyh = in nv50_dac_atomic_enable() local
507 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); in nv50_dac_atomic_enable()
508 asyh->or.depth = 0; in nv50_dac_atomic_enable()
964 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); in nv50_msto_atomic_check() local
984 asyh->or.bpc = connector->display_info.bpc; in nv50_msto_atomic_check()
985 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4); in nv50_msto_atomic_check()
998 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn); in nv50_msto_atomic_check()
1002 asyh->dp.tu = slots; in nv50_msto_atomic_check()
1023 struct nv50_head_atom *asyh = in nv50_msto_atomic_enable() local
1059 mstm->outp->update(mstm->outp, head->base.index, asyh, proto, in nv50_msto_atomic_enable()
1060 nv50_dp_bpc_to_depth(asyh->or.bpc)); in nv50_msto_atomic_enable()
1533 struct nv50_head_atom *asyh, u8 proto, u8 depth) in nv50_sor_update() argument
1538 if (!asyh) { in nv50_sor_update()
1545 asyh->or.depth = depth; in nv50_sor_update()
1548 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh); in nv50_sor_update()
1601 struct nv50_head *head, struct nv50_head_atom *asyh) in nv50_sor_dp_watermark_sst() argument
1616 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke; in nv50_sor_dp_watermark_sst()
1617 unsigned rasterWidth = asyh->mode.h.active; in nv50_sor_dp_watermark_sst()
1618 unsigned depth = asyh->or.bpc * 3; in nv50_sor_dp_watermark_sst()
1620 u64 pixelClockHz = asyh->mode.clock * 1000; in nv50_sor_dp_watermark_sst()
1740 struct nv50_head_atom *asyh = in nv50_sor_atomic_enable() local
1742 struct drm_display_mode *mode = &asyh->state.adjusted_mode; in nv50_sor_atomic_enable()
1814 if (asyh->or.bpc == 8) in nv50_sor_atomic_enable()
1821 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc); in nv50_sor_atomic_enable()
1822 nv50_sor_dp_watermark_sst(nv_encoder, head, asyh); in nv50_sor_atomic_enable()
1823 depth = nv50_dp_bpc_to_depth(asyh->or.bpc); in nv50_sor_atomic_enable()
1846 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth); in nv50_sor_atomic_enable()
1977 struct nv50_head_atom *asyh = in nv50_pior_atomic_enable() local
1990 switch (asyh->or.bpc) { in nv50_pior_atomic_enable()
1991 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break; in nv50_pior_atomic_enable()
1992 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break; in nv50_pior_atomic_enable()
1993 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break; in nv50_pior_atomic_enable()
1994 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break; in nv50_pior_atomic_enable()
2006 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6); in nv50_pior_atomic_enable()
2013 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh); in nv50_pior_atomic_enable()
2190 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2194 asyh->clr.mask, asyh->set.mask); in nv50_disp_atomic_commit_tail()
2201 if (asyh->clr.mask) { in nv50_disp_atomic_commit_tail()
2202 nv50_head_flush_clr(head, asyh, atom->flush_disable); in nv50_disp_atomic_commit_tail()
2273 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2277 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2279 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2280 nv50_head_flush_set(head, asyh); in nv50_disp_atomic_commit_tail()
2324 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_commit_tail() local
2328 asyh->set.mask, asyh->clr.mask); in nv50_disp_atomic_commit_tail()
2330 if (asyh->set.mask) { in nv50_disp_atomic_commit_tail()
2331 nv50_head_flush_set_wndw(head, asyh); in nv50_disp_atomic_commit_tail()
2564 struct nv50_head_atom *asyh; in nv50_disp_atomic_check() local
2575 asyh = nv50_head_atom(new_crtc_state); in nv50_disp_atomic_check()
2576 core->func->head->static_wndw_map(head, asyh); in nv50_disp_atomic_check()