Lines Matching +full:gop +full:- +full:port +full:- +full:id
32 #include <linux/dma-mapping.h>
84 chan->device = device;
95 &chan->user);
97 ret = nvif_object_map(&chan->user, NULL, 0);
99 nvif_object_dtor(&chan->user);
109 return -ENOSYS;
115 nvif_object_dtor(&chan->user);
125 nvif_object_dtor(&dmac->vram);
126 nvif_object_dtor(&dmac->sync);
128 nv50_chan_destroy(&dmac->base);
130 nvif_mem_dtor(&dmac->push.mem);
138 dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr;
139 if (dmac->put != dmac->cur) {
143 if (dmac->push.mem.type & NVIF_MEM_VRAM) {
144 struct nvif_device *device = dmac->base.device;
145 nvif_wr32(&device->object, 0x070000, 0x00000001);
147 if (!(nvif_rd32(&device->object, 0x070000) & 0x00000002))
152 NVIF_WV32(&dmac->base.user, NV507C, PUT, PTR, dmac->cur);
153 dmac->put = dmac->cur;
156 push->bgn = push->cur;
162 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
163 if (get > dmac->cur) /* NVIDIA stay 5 away from GET, do the same. */
164 return get - dmac->cur - 5;
165 return dmac->max - dmac->cur;
174 u32 get = NVIF_RV32(&dmac->base.user, NV507C, GET, PTR);
176 /* Corner-case, HW idle, but non-committed work pending. */
177 if (dmac->put == 0)
178 nv50_dmac_kick(&dmac->push);
180 if (nvif_msec(dmac->base.device, 2000,
181 if (NVIF_TV32(&dmac->base.user, NV507C, GET, PTR, >, 0))
184 return -ETIMEDOUT;
187 PUSH_RSVD(&dmac->push, PUSH_JUMP(&dmac->push, 0));
188 dmac->cur = 0;
198 if (WARN_ON(size > dmac->max))
199 return -EINVAL;
201 dmac->cur = push->cur - (u32 __iomem *)dmac->push.mem.object.map.ptr;
202 if (dmac->cur + size >= dmac->max) {
207 push->cur = dmac->push.mem.object.map.ptr;
208 push->cur = push->cur + dmac->cur;
212 if (nvif_msec(dmac->base.device, 2000,
217 return -ETIMEDOUT;
220 push->bgn = dmac->push.mem.object.map.ptr;
221 push->bgn = push->bgn + dmac->cur;
222 push->cur = push->bgn;
223 push->end = push->cur + free;
228 static int nv50_dmac_vram_pushbuf = -1;
236 struct nvif_device *device = &drm->device;
237 struct nvif_object *disp = &drm->display->disp.object;
242 /* Pascal added support for 47-bit physical addresses, but some
243 * parts of EVO still only accept 40-bit PAs.
252 (nv50_dmac_vram_pushbuf < 0 && device->info.family == NV_DEVICE_INFO_V0_PASCAL))
255 ret = nvif_mem_ctor_map(&drm->mmu, "kmsChanPush", type, 0x1000, &dmac->push.mem);
259 dmac->push.wait = nv50_dmac_wait;
260 dmac->push.kick = nv50_dmac_kick;
261 dmac->push.bgn = dmac->push.mem.object.map.ptr;
262 dmac->push.cur = dmac->push.bgn;
263 dmac->push.end = dmac->push.bgn;
264 dmac->max = 0x1000/4 - 1;
269 if (disp->oclass < GV100_DISP)
270 dmac->max -= 12;
272 args->pushbuf = nvif_handle(&dmac->push.mem.object);
275 &dmac->base);
283 if (disp->oclass >= GB202_DISP) {
287 dmac->sync.handle = NV50_DISP_HANDLE_SYNCBUF;
288 dmac->vram.handle = NV50_DISP_HANDLE_VRAM;
292 ret = nvif_object_ctor(&dmac->base.user, "kmsSyncCtxDma", NV50_DISP_HANDLE_SYNCBUF,
300 &dmac->sync);
304 ret = nvif_object_ctor(&dmac->base.user, "kmsVramCtxDma", NV50_DISP_HANDLE_VRAM,
310 .limit = device->info.ram_user - 1,
312 &dmac->vram);
327 outp->base.base.name, outp->caps.dp_interlace);
336 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
337 struct drm_display_mode *mode = &crtc_state->mode;
338 struct drm_connector *connector = conn_state->connector;
340 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
342 NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
343 asyc->scaler.full = false;
347 if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
348 switch (connector->connector_type) {
355 if (mode->hdisplay == native_mode->hdisplay &&
356 mode->vdisplay == native_mode->vdisplay &&
357 mode->type & DRM_MODE_TYPE_DRIVER)
360 asyc->scaler.full = true;
371 crtc_state->mode_changed = true;
382 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
385 switch (nv_encoder->dcb->type) {
387 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw;
390 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
393 while (asyh->or.bpc > 6) {
394 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
398 asyh->or.bpc -= 2;
411 struct drm_connector *connector = conn_state->connector;
417 nv_connector->native_mode);
421 if (crtc_state->mode_changed || crtc_state->connectors_changed)
422 asyh->or.bpc = connector->display_info.bpc;
439 if (connector_state->best_encoder == encoder)
455 if (connector_state->best_encoder == encoder)
467 const u32 mask = drm_encoder_mask(&outp->base.base);
471 if (crtc_state->encoder_mask & mask)
485 struct nv50_core *core = nv50_disp(encoder->dev)->core;
488 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
489 nv_encoder->crtc = NULL;
498 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
499 struct nv50_core *core = nv50_disp(encoder->dev)->core;
502 switch (nv_crtc->index) {
514 if (!nvif_outp_acquired(&nv_encoder->outp))
515 nvif_outp_acquire_dac(&nv_encoder->outp);
517 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
518 asyh->or.depth = 0;
520 nv_encoder->crtc = &nv_crtc->base;
530 loadval = nouveau_drm(encoder->dev)->vbios.dactestval;
534 ret = nvif_outp_load_detect(&nv_encoder->outp, loadval);
554 nvif_outp_dtor(&nv_encoder->outp);
568 struct drm_connector *connector = &nv_encoder->conn->base;
569 struct nouveau_drm *drm = nouveau_drm(connector->dev);
573 struct dcb_output *dcbe = nv_encoder->dcb;
576 bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
578 nv_encoder->i2c = &bus->i2c;
581 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
582 "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
593 nv50_audio_component_eld_notify(struct drm_audio_component *acomp, int port,
596 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
597 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
598 port, dev_id);
602 nv50_audio_component_get_eld(struct device *kdev, int port, int dev_id,
613 mutex_lock(&drm->audio.lock);
615 drm_for_each_encoder(encoder, drm->dev) {
618 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
622 nv_connector = nv_encoder->conn;
623 nv_crtc = nouveau_crtc(nv_encoder->crtc);
625 if (!nv_crtc || nv_encoder->outp.or.id != port || nv_crtc->index != dev_id)
628 *enabled = nv_encoder->audio.enabled;
630 ret = drm_eld_size(nv_connector->base.eld);
631 memcpy(buf, nv_connector->base.eld,
637 mutex_unlock(&drm->audio.lock);
654 return -ENOMEM;
656 drm_modeset_lock_all(drm->dev);
657 acomp->ops = &nv50_audio_component_ops;
658 acomp->dev = kdev;
659 drm->audio.component = acomp;
660 drm_modeset_unlock_all(drm->dev);
671 drm_modeset_lock_all(drm->dev);
672 drm->audio.component = NULL;
673 acomp->ops = NULL;
674 acomp->dev = NULL;
675 drm_modeset_unlock_all(drm->dev);
686 if (component_add(drm->dev->dev, &nv50_audio_component_bind_ops))
689 drm->audio.component_registered = true;
690 mutex_init(&drm->audio.lock);
696 if (!drm->audio.component_registered)
699 component_del(drm->dev->dev, &nv50_audio_component_bind_ops);
700 drm->audio.component_registered = false;
701 mutex_destroy(&drm->audio.lock);
710 struct nv50_disp *disp = nv50_disp(encoder->dev);
712 if (disp->disp->object.oclass <= GT200_DISP ||
713 disp->disp->object.oclass == GT206_DISP)
716 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
719 switch (nv_encoder->dcb->type) {
734 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
736 struct nvif_outp *outp = &nv_encoder->outp;
741 mutex_lock(&drm->audio.lock);
742 if (nv_encoder->audio.enabled) {
743 nv_encoder->audio.enabled = false;
744 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, NULL, 0);
746 mutex_unlock(&drm->audio.lock);
748 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
756 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
758 struct nvif_outp *outp = &nv_encoder->outp;
760 if (!nv50_audio_supported(encoder) || !nv_connector->base.display_info.has_audio)
763 mutex_lock(&drm->audio.lock);
765 nvif_outp_hda_eld(&nv_encoder->outp, nv_crtc->index, nv_connector->base.eld,
766 drm_eld_size(nv_connector->base.eld));
767 nv_encoder->audio.enabled = true;
769 mutex_unlock(&drm->audio.lock);
771 nv50_audio_component_eld_notify(drm->audio.component, outp->or.id, nv_crtc->index);
782 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
784 struct drm_hdmi_info *hdmi = &nv_connector->base.display_info.hdmi;
789 const u8 data_len = __member_size(args->data);
792 max_ac_packet = mode->htotal - mode->hdisplay;
793 max_ac_packet -= rekey;
794 max_ac_packet -= 18; /* constant from tegra */
797 if (nv_encoder->i2c && hdmi->scdc.scrambling.supported) {
798 const bool high_tmds_clock_ratio = mode->clock > 340000;
801 ret = drm_scdc_readb(nv_encoder->i2c, SCDC_TMDS_CONFIG, &scdc);
808 if (high_tmds_clock_ratio || hdmi->scdc.scrambling.low_rates)
813 ret = drm_scdc_writeb(nv_encoder->i2c, SCDC_TMDS_CONFIG, scdc);
819 ret = nvif_outp_hdmi(&nv_encoder->outp, nv_crtc->index, true, max_ac_packet, rekey,
820 mode->clock, hdmi->scdc.supported, hdmi->scdc.scrambling.supported,
821 hdmi->scdc.scrambling.low_rates);
826 args->version = 0;
827 args->head = nv_crtc->index;
829 if (!drm_hdmi_avi_infoframe_from_display_mode(&infoframe.avi, &nv_connector->base, mode)) {
830 drm_hdmi_avi_infoframe_quant_range(&infoframe.avi, &nv_connector->base, mode,
833 size = hdmi_infoframe_pack(&infoframe, args->data, data_len);
838 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_AVI, args, size);
841 memset(args->data, 0, data_len);
843 &nv_connector->base, mode))
844 size = hdmi_infoframe_pack(&infoframe, args->data, data_len);
848 nvif_outp_infoframe(&nv_encoder->outp, NVIF_OUTP_INFOFRAME_V0_VSI, args, size);
850 nv_encoder->hdmi.enabled = true;
862 struct drm_dp_mst_port *port;
885 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
889 if (!msto->mstc)
891 return msto->mstc->mstm->outp;
900 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
902 drm_atomic_get_mst_payload_state(new_mst_state, msto->mstc->port);
906 drm_atomic_get_mst_payload_state(old_mst_state, msto->mstc->port);
907 struct nv50_mstc *mstc = msto->mstc;
908 struct nv50_mstm *mstm = mstc->mstm;
910 NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
912 if (msto->disabled) {
913 if (msto->head->func->display_id) {
914 nvif_outp_dp_mst_id_put(&mstm->outp->outp, msto->display_id);
915 msto->display_id = 0;
918 msto->mstc = NULL;
919 msto->disabled = false;
921 } else if (msto->enabled) {
923 msto->enabled = false;
933 struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
934 struct nv50_mstc *mstc = msto->mstc;
935 struct nv50_mstm *mstm = mstc->mstm;
939 NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
941 payload = drm_atomic_get_mst_payload_state(mst_state, mstc->port);
943 if (msto->disabled) {
945 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
948 if (msto->enabled)
953 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index,
954 payload->vc_start_slot, payload->time_slots,
955 payload->pbn,
956 payload->time_slots * dfixed_trunc(mst_state->pbn_div));
958 nvif_outp_dp_mst_vcpi(&mstm->outp->outp, msto->head->base.index, 0, 0, 0, 0);
967 struct drm_atomic_state *state = crtc_state->state;
968 struct drm_connector *connector = conn_state->connector;
971 struct nv50_mstm *mstm = mstc->mstm;
977 mstc->native);
989 if (!state->duplicated) {
990 const int clock = crtc_state->adjusted_mode.clock;
992 asyh->or.bpc = connector->display_info.bpc;
993 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
996 mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
1000 if (!mst_state->pbn_div.full) {
1001 struct nouveau_encoder *outp = mstc->mstm->outp;
1003 mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr);
1006 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
1010 asyh->dp.tu = slots;
1030 struct nv50_head *head = msto->head;
1032 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &head->base.base));
1039 drm_connector_list_iter_begin(encoder->dev, &conn_iter);
1041 if (connector->state->best_encoder == &msto->encoder) {
1043 mstm = mstc->mstm;
1052 if (!mstm->links++) {
1053 nvif_outp_acquire_sor(&mstm->outp->outp, false /*TODO: MST audio... */);
1054 nouveau_dp_train(mstm->outp, true, 0, 0);
1057 if (head->func->display_id) {
1058 if (!WARN_ON(nvif_outp_dp_mst_id_get(&mstm->outp->outp, &msto->display_id)))
1059 head->func->display_id(head, msto->display_id);
1062 if (mstm->outp->outp.or.link & 1)
1067 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1068 nv50_dp_bpc_to_depth(asyh->or.bpc));
1070 msto->mstc = mstc;
1071 msto->enabled = true;
1072 mstm->modified = true;
1079 struct nv50_mstc *mstc = msto->mstc;
1080 struct nv50_mstm *mstm = mstc->mstm;
1082 if (msto->head->func->display_id)
1083 msto->head->func->display_id(msto->head, 0);
1085 mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
1086 mstm->modified = true;
1087 if (!--mstm->links)
1088 mstm->disabled = true;
1089 msto->disabled = true;
1103 drm_encoder_cleanup(&msto->encoder);
1113 nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id)
1120 return ERR_PTR(-ENOMEM);
1122 ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
1123 DRM_MODE_ENCODER_DPMST, "mst-%d", id);
1129 drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
1130 msto->encoder.possible_crtcs = drm_crtc_mask(&head->base.base);
1131 msto->head = head;
1142 struct drm_crtc *crtc = connector_state->crtc;
1144 if (!(mstc->mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1147 return &nv50_head(crtc)->msto->encoder;
1155 struct nouveau_encoder *outp = mstc->mstm->outp;
1170 mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
1171 drm_connector_update_edid_property(&mstc->connector, mstc->edid);
1172 if (mstc->edid)
1173 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
1181 if (connector->display_info.bpc)
1182 connector->display_info.bpc =
1183 clamp(connector->display_info.bpc, 6U, 8U);
1185 connector->display_info.bpc = 8;
1187 if (mstc->native)
1188 drm_mode_destroy(mstc->connector.dev, mstc->native);
1189 mstc->native = nouveau_conn_native_mode(&mstc->connector);
1198 struct drm_dp_mst_topology_mgr *mgr = &mstc->mstm->mgr;
1200 return drm_dp_atomic_release_time_slots(state, mgr, mstc->port);
1213 ret = pm_runtime_get_sync(connector->dev->dev);
1214 if (ret < 0 && ret != -EACCES) {
1215 pm_runtime_put_autosuspend(connector->dev->dev);
1219 ret = drm_dp_mst_detect_port(connector, ctx, mstc->port->mgr,
1220 mstc->port);
1225 pm_runtime_mark_last_busy(connector->dev->dev);
1226 pm_runtime_put_autosuspend(connector->dev->dev);
1244 drm_connector_cleanup(&mstc->connector);
1245 drm_dp_mst_put_port_malloc(mstc->port);
1262 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
1265 struct drm_device *dev = mstm->outp->base.base.dev;
1271 return -ENOMEM;
1272 mstc->mstm = mstm;
1273 mstc->port = port;
1275 ret = drm_connector_dynamic_init(dev, &mstc->connector, &nv50_mstc,
1283 drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
1285 mstc->connector.funcs->reset(&mstc->connector);
1286 nouveau_conn_attach_properties(&mstc->connector);
1289 if (!(mstm->outp->dcb->heads & drm_crtc_mask(crtc)))
1292 drm_connector_attach_encoder(&mstc->connector,
1293 &nv50_head(crtc)->msto->encoder);
1296 drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
1297 drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
1298 drm_connector_set_path_property(&mstc->connector, path);
1299 drm_dp_mst_get_port_malloc(port);
1308 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1311 NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
1312 drm_dp_check_act_status(&mstm->mgr);
1314 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1315 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1317 struct nv50_mstc *mstc = msto->mstc;
1318 if (mstc && mstc->mstm == mstm)
1319 nv50_msto_cleanup(state, mst_state, &mstm->mgr, msto);
1323 if (mstm->disabled) {
1324 nouveau_dp_power_down(mstm->outp);
1325 nvif_outp_release(&mstm->outp->outp);
1326 mstm->disabled = false;
1329 mstm->modified = false;
1337 struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
1340 NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
1343 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1344 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1346 struct nv50_mstc *mstc = msto->mstc;
1347 if (mstc && mstc->mstm == mstm && msto->disabled)
1348 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1355 drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
1356 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
1358 struct nv50_mstc *mstc = msto->mstc;
1359 if (mstc && mstc->mstm == mstm && !msto->disabled)
1360 nv50_msto_prepare(state, mst_state, &mstm->mgr, msto);
1367 struct drm_dp_mst_port *port, const char *path)
1373 ret = nv50_mstc_new(mstm, port, path, &mstc);
1377 return &mstc->connector;
1390 struct drm_dp_aux *aux = &nv_connector->aux;
1404 drm_dp_mst_hpd_irq_handle_event(&mstm->mgr, esi, ack, &handled);
1415 drm_dp_mst_hpd_irq_send_new_request(&mstm->mgr);
1420 nv_connector->base.name, rc);
1428 mstm->is_mst = false;
1429 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
1435 struct nv50_mstm *mstm = outp->dp.mstm;
1439 if (!mstm || !mstm->can_mst)
1442 aux = mstm->mgr.aux;
1452 ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, true);
1456 mstm->is_mst = true;
1463 struct nv50_mstm *mstm = outp->dp.mstm;
1470 * path to protect mstm->is_mst without potentially deadlocking
1472 mutex_lock(&outp->dp.hpd_irq_lock);
1473 mstm->suspended = true;
1474 mutex_unlock(&outp->dp.hpd_irq_lock);
1476 if (mstm->is_mst)
1477 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
1483 struct nv50_mstm *mstm = outp->dp.mstm;
1489 if (mstm->is_mst) {
1490 ret = drm_dp_mst_topology_mgr_resume(&mstm->mgr, !runtime);
1491 if (ret == -1)
1495 mutex_lock(&outp->dp.hpd_irq_lock);
1496 mstm->suspended = false;
1497 mutex_unlock(&outp->dp.hpd_irq_lock);
1499 if (ret == -1)
1500 drm_kms_helper_hotplug_event(mstm->mgr.dev);
1508 drm_dp_mst_topology_mgr_destroy(&mstm->mgr);
1518 const int max_payloads = hweight8(outp->dcb->heads);
1519 struct drm_device *dev = outp->base.base.dev;
1524 return -ENOMEM;
1525 mstm->outp = outp;
1526 mstm->mgr.cbs = &nv50_mstm;
1528 ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
1543 struct nv50_disp *disp = nv50_disp(nv_encoder->base.base.dev);
1544 struct nv50_core *core = disp->core;
1547 nv_encoder->ctrl &= ~BIT(head);
1548 if (NVDEF_TEST(nv_encoder->ctrl, NV507D, SOR_SET_CONTROL, OWNER, ==, NONE))
1549 nv_encoder->ctrl = 0;
1551 nv_encoder->ctrl |= NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto);
1552 nv_encoder->ctrl |= BIT(head);
1553 asyh->or.depth = depth;
1556 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1559 /* TODO: Should we extend this to PWM-only backlights?
1568 struct nv50_head *head = nv50_head(nv_encoder->crtc);
1571 struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
1572 struct nouveau_backlight *backlight = nv_connector->backlight;
1573 struct drm_dp_aux *aux = &nv_connector->aux;
1576 if (backlight && backlight->uses_dpcd) {
1577 ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
1580 nv_connector->base.base.id, nv_connector->base.name, ret);
1584 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && nv_encoder->hdmi.enabled) {
1585 nvif_outp_hdmi(&nv_encoder->outp, head->base.index,
1587 nv_encoder->hdmi.enabled = false;
1590 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1593 if (head->func->display_id)
1594 head->func->display_id(head, 0);
1596 nv_encoder->update(nv_encoder, head->base.index, NULL, 0, 0);
1597 nv50_audio_disable(encoder, &head->base);
1598 nv_encoder->crtc = NULL;
1611 bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP;
1612 u64 minRate = outp->dp.link_bw * 1000;
1624 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1625 unsigned rasterWidth = asyh->mode.h.active;
1626 unsigned depth = asyh->or.bpc * 3;
1628 u64 pixelClockHz = asyh->mode.clock * 1000;
1630 u32 numLanesPerLink = outp->dp.link_nr;
1638 if (outp->outp.info.dp.increased_wm) {
1643 if ((pixelClockHz * depth) >= (8 * minRate * outp->dp.link_nr * DSC_FACTOR))
1653 ((pixelClockHz * depth) < div_u64(8 * minRate * outp->dp.link_nr * DSC_FACTOR, 64)))
1665 ratioF = div_u64(ratioF, 8 * (u64) minRate * outp->dp.link_nr);
1670 watermarkF = div_u64(ratioF * tuSize * (PrecisionFactor - ratioF), PrecisionFactor);
1676 numSymbolsPerLine = div_u64(surfaceWidth * depth, 8 * outp->dp.link_nr * DSC_FACTOR);
1699 PixelSteeringBits = remain ? div_u64((numLanesPerLink - remain) * depth, DSC_FACTOR) : 0;
1706 if (WARN_ON(MinHBlank > rasterWidth - surfaceWidth))
1709 // Bug 702290 - Active Width should be greater than 60
1714 hblank_symbols = (s32)(div_u64((u64)(rasterWidth - surfaceWidth - MinHBlank) * minRate, pixelClockHz));
1717 hblank_symbols -= 1; //Stuffer latency to send BS
1718 hblank_symbols -= 3; //SPKT latency to send data to stuffer
1720 hblank_symbols -= numLanesPerLink == 1 ? 9 : numLanesPerLink == 2 ? 6 : 3;
1725 // # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - SetRasterBlankStart.X - 40) * link_clk / pclk) - Y - 1;
1733 vblank_symbols = (s32)((div_u64((u64)(surfaceWidth - 40) * minRate, pixelClockHz))) - 1;
1735 vblank_symbols -= numLanesPerLink == 1 ? 39 : numLanesPerLink == 2 ? 21 : 12;
1740 return nvif_outp_dp_sst(&outp->outp, head->base.index, waterMark, hBlankSym, vBlankSym);
1749 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1750 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1751 struct nv50_disp *disp = nv50_disp(encoder->dev);
1752 struct nv50_head *head = nv50_head(&nv_crtc->base);
1753 struct nvif_outp *outp = &nv_encoder->outp;
1754 struct drm_device *dev = encoder->dev;
1760 struct nvbios *bios = &drm->vbios;
1766 nv_encoder->crtc = &nv_crtc->base;
1768 if ((disp->disp->object.oclass == GT214_DISP ||
1769 disp->disp->object.oclass >= GF110_DISP) &&
1770 nv_encoder->dcb->type != DCB_OUTPUT_LVDS &&
1771 nv_connector->base.display_info.has_audio)
1777 switch (nv_encoder->dcb->type) {
1779 if (disp->disp->object.oclass != NV50_DISP &&
1780 nv_connector->base.display_info.is_hdmi)
1783 if (nv_encoder->outp.or.link & 1) {
1785 /* Only enable dual-link if:
1786 * - Need to (i.e. rate > 165MHz)
1787 * - DCB says we can
1788 * - Not an HDMI monitor, since there's no dual-link
1791 if (mode->clock >= 165000 &&
1792 nv_encoder->dcb->duallink_possible &&
1793 !nv_connector->base.display_info.is_hdmi)
1802 if (bios->fp_no_ddc) {
1803 lvds_dual = bios->fp.dual_link;
1804 lvds_8bpc = bios->fp.if_is_24bit;
1806 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1807 if (((u8 *)nv_connector->edid)[121] == 2)
1810 if (mode->clock >= bios->fp.duallink_transition_clk) {
1815 if (bios->fp.strapless_is_24bit & 2)
1818 if (bios->fp.strapless_is_24bit & 1)
1822 if (asyh->or.bpc == 8)
1826 nvif_outp_lvds(&nv_encoder->outp, lvds_dual, lvds_8bpc);
1829 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1831 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1833 if (nv_encoder->outp.or.link & 1)
1839 backlight = nv_connector->backlight;
1840 if (backlight && backlight->uses_dpcd)
1841 drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
1842 backlight->dev->props.brightness);
1851 if (head->func->display_id)
1852 head->func->display_id(head, BIT(nv_encoder->outp.id));
1854 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1869 nv50_mstm_del(&nv_encoder->dp.mstm);
1872 if (nv_encoder->dcb->type == DCB_OUTPUT_DP)
1873 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
1875 nvif_outp_dtor(&nv_encoder->outp);
1887 struct drm_connector *connector = &nv_encoder->conn->base;
1889 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1892 struct dcb_output *dcbe = nv_encoder->dcb;
1893 struct nv50_disp *disp = nv50_disp(connector->dev);
1896 switch (dcbe->type) {
1905 nv_encoder->update = nv50_sor_update;
1908 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
1909 "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
1914 disp->core->func->sor->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
1917 if (dcbe->type == DCB_OUTPUT_DP) {
1918 mutex_init(&nv_encoder->dp.hpd_irq_lock);
1920 if (disp->disp->object.oclass < GF110_DISP) {
1921 /* HW has no support for address-only
1923 * use custom I2C-over-AUX code.
1927 aux = nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
1929 return -EINVAL;
1931 nv_encoder->i2c = &aux->i2c;
1933 nv_encoder->i2c = &nv_connector->aux.ddc;
1936 if (nv_connector->type != DCB_CONNECTOR_eDP && nv_encoder->outp.info.dp.mst) {
1937 ret = nv50_mstm_new(nv_encoder, &nv_connector->aux,
1938 16, nv_connector->base.base.id,
1939 &nv_encoder->dp.mstm);
1944 if (nv_encoder->outp.info.ddc != NVIF_OUTP_DDC_INVALID) {
1946 nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1948 nv_encoder->i2c = &bus->i2c;
1965 crtc_state->adjusted_mode.clock *= 2;
1973 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1976 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, NULL);
1977 nv_encoder->crtc = NULL;
1986 nv50_head_atom(drm_atomic_get_new_crtc_state(state, &nv_crtc->base));
1987 struct nv50_core *core = nv50_disp(encoder->dev)->core;
1990 switch (nv_crtc->index) {
1998 switch (asyh->or.bpc) {
1999 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
2000 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
2001 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
2002 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
2005 if (!nvif_outp_acquired(&nv_encoder->outp))
2006 nvif_outp_acquire_pior(&nv_encoder->outp);
2008 switch (nv_encoder->dcb->type) {
2014 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6);
2021 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2022 nv_encoder->crtc = &nv_crtc->base;
2037 nvif_outp_dtor(&nv_encoder->outp);
2041 mutex_destroy(&nv_encoder->dp.hpd_irq_lock);
2053 struct drm_connector *connector = &nv_encoder->conn->base;
2054 struct drm_device *dev = connector->dev;
2062 struct dcb_output *dcbe = nv_encoder->dcb;
2065 switch (dcbe->type) {
2067 bus = nvkm_i2c_bus_find(i2c, nv_encoder->outp.info.ddc);
2068 ddc = bus ? &bus->i2c : NULL;
2072 aux = nvkm_i2c_aux_find(i2c, nv_encoder->outp.info.dp.aux);
2073 ddc = aux ? &aux->i2c : NULL;
2077 return -ENODEV;
2080 nv_encoder->i2c = ddc;
2082 mutex_init(&nv_encoder->dp.hpd_irq_lock);
2085 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
2086 "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
2091 disp->core->func->pior->get_caps(disp, nv_encoder, ffs(dcbe->or) - 1);
2106 struct nouveau_drm *drm = nouveau_drm(state->dev);
2107 struct nv50_disp *disp = nv50_disp(drm->dev);
2109 struct nv50_core *core = disp->core;
2118 if (mstm->modified)
2122 core->func->ntfy_init(disp->sync, NV50_DISP_CORE_NTFY);
2123 core->func->update(core, interlock, true);
2124 if (core->func->ntfy_wait_done(disp->sync, NV50_DISP_CORE_NTFY,
2125 disp->core->chan.base.device))
2130 if (mstm->modified)
2134 list_for_each_entry(outp, &atom->outp, head) {
2135 if (outp->encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2136 struct nouveau_encoder *nv_encoder = nouveau_encoder(outp->encoder);
2138 if (outp->enabled) {
2139 nv50_audio_enable(outp->encoder, nouveau_crtc(nv_encoder->crtc),
2140 nv_encoder->conn, NULL, NULL);
2141 outp->enabled = outp->disabled = false;
2143 if (outp->disabled) {
2144 nvif_outp_release(&nv_encoder->outp);
2145 outp->disabled = false;
2161 if (interlock[wndw->interlock.type] & wndw->interlock.data) {
2162 if (wndw->func->update)
2163 wndw->func->update(wndw, interlock);
2171 struct drm_device *dev = state->dev;
2179 struct nv50_core *core = disp->core;
2185 NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
2193 if (atom->lock_core)
2194 mutex_lock(&disp->mutex);
2201 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
2202 asyh->clr.mask, asyh->set.mask);
2204 if (old_crtc_state->active && !new_crtc_state->active) {
2205 pm_runtime_put_noidle(dev->dev);
2209 if (asyh->clr.mask) {
2210 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2220 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
2221 asyw->clr.mask, asyw->set.mask);
2222 if (!asyw->clr.mask)
2225 nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
2229 list_for_each_entry(outp, &atom->outp, head) {
2233 encoder = outp->encoder;
2234 help = encoder->helper_private;
2236 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
2237 outp->clr.mask, outp->set.mask);
2239 if (outp->clr.mask) {
2240 help->atomic_disable(encoder, state);
2241 outp->disabled = true;
2248 if (atom->flush_disable) {
2262 list_for_each_entry(outp, &atom->outp, head) {
2266 encoder = outp->encoder;
2267 help = encoder->helper_private;
2269 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
2270 outp->set.mask, outp->clr.mask);
2272 if (outp->set.mask) {
2273 help->atomic_enable(encoder, state);
2274 outp->enabled = true;
2284 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2285 asyh->set.mask, asyh->clr.mask);
2287 if (asyh->set.mask) {
2292 if (new_crtc_state->active) {
2293 if (!old_crtc_state->active) {
2295 pm_runtime_get_noresume(dev->dev);
2297 if (new_crtc_state->event)
2302 /* Update window->head assignment.
2308 * supports non-fixed mappings).
2310 if (core->assign_windows) {
2311 core->func->wndw.owner(core);
2313 core->assign_windows = false;
2322 * The EFI GOP driver on newer GPUs configures window channels with a
2335 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
2336 asyh->set.mask, asyh->clr.mask);
2338 if (asyh->set.mask) {
2349 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
2350 asyw->set.mask, asyw->clr.mask);
2351 if ( !asyw->set.mask &&
2352 (!asyw->clr.mask || atom->flush_disable))
2365 !atom->state.legacy_cursor_update)
2368 disp->core->func->update(disp->core, interlock, false);
2371 if (atom->lock_core)
2372 mutex_unlock(&disp->mutex);
2374 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2375 list_del(&outp->head);
2385 NV_ERROR(drm, "%s: timeout\n", plane->name);
2389 if (new_crtc_state->event) {
2392 if (new_crtc_state->active)
2394 spin_lock_irqsave(&crtc->dev->event_lock, flags);
2395 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
2396 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
2398 new_crtc_state->event = NULL;
2399 if (new_crtc_state->active)
2414 pm_runtime_mark_last_busy(dev->dev);
2415 pm_runtime_put_autosuspend(dev->dev);
2434 ret = pm_runtime_get_sync(dev->dev);
2435 if (ret < 0 && ret != -EACCES) {
2436 pm_runtime_put_autosuspend(dev->dev);
2444 INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
2464 if (asyw->set.image)
2474 pm_runtime_get_noresume(dev->dev);
2477 queue_work(system_unbound_wq, &state->commit_work);
2485 pm_runtime_put_autosuspend(dev->dev);
2494 list_for_each_entry(outp, &atom->outp, head) {
2495 if (outp->encoder == encoder)
2501 return ERR_PTR(-ENOMEM);
2503 list_add(&outp->head, &atom->outp);
2504 outp->encoder = encoder;
2512 struct drm_encoder *encoder = old_connector_state->best_encoder;
2517 if (!(crtc = old_connector_state->crtc))
2520 old_crtc_state = drm_atomic_get_old_crtc_state(&atom->state, crtc);
2521 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2522 if (old_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2527 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST ||
2528 nouveau_encoder(outp->encoder)->dcb->type == DCB_OUTPUT_DP)
2529 atom->flush_disable = true;
2530 outp->clr.ctrl = true;
2531 atom->lock_core = true;
2541 struct drm_encoder *encoder = connector_state->best_encoder;
2546 if (!(crtc = connector_state->crtc))
2549 new_crtc_state = drm_atomic_get_new_crtc_state(&atom->state, crtc);
2550 if (new_crtc_state->active && drm_atomic_crtc_needs_modeset(new_crtc_state)) {
2555 outp->set.ctrl = true;
2556 atom->lock_core = true;
2566 struct nv50_core *core = nv50_disp(dev)->core;
2575 if (core->assign_windows && core->func->head->static_wndw_map) {
2584 core->func->head->static_wndw_map(head, asyh);
2588 /* We need to handle colour management on a per-plane basis. */
2590 if (new_crtc_state->color_mgmt_changed) {
2626 list_for_each_entry_safe(outp, outt, &atom->outp, head) {
2627 list_del(&outp->head);
2638 drm_atomic_state_default_release(&atom->state);
2647 drm_atomic_state_init(dev, &atom->state) < 0) {
2651 INIT_LIST_HEAD(&atom->outp);
2652 return &atom->state;
2680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2681 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST)
2685 if (!runtime && !drm->headless)
2686 cancel_work_sync(&drm->hpd_work);
2697 const u32 encoder_mask = drm_encoder_mask(&outp->base.base);
2703 switch (outp->dcb->type) {
2705 ret = nvif_outp_inherit_tmds(&outp->outp, &proto);
2708 ret = nvif_outp_inherit_dp(&outp->outp, &proto);
2711 ret = nvif_outp_inherit_lvds(&outp->outp, &proto);
2714 ret = nvif_outp_inherit_rgb_crt(&outp->outp, &proto);
2718 outp->base.base.name);
2729 if (crtc->index != head_idx)
2732 armh = nv50_head_atom(crtc->state);
2742 if (nouveau_connector(conn)->index == outp->dcb->connector) {
2751 armh->state.encoder_mask = encoder_mask;
2752 armh->state.connector_mask = drm_connector_mask(conn);
2753 armh->state.active = true;
2754 armh->state.enable = true;
2755 pm_runtime_get_noresume(dev->dev);
2757 outp->crtc = crtc;
2758 outp->ctrl = NVVAL(NV507D, SOR_SET_CONTROL, PROTOCOL, proto) | BIT(crtc->index);
2761 conn->state->crtc = crtc;
2762 conn->state->best_encoder = &outp->base.base;
2769 struct drm_device *dev = drm->dev;
2778 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST)
2790 struct nv50_core *core = nv50_disp(dev)->core;
2794 core->func->init(core);
2796 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2797 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
2817 nvif_object_unmap(&disp->caps);
2818 nvif_object_dtor(&disp->caps);
2819 nv50_core_del(&disp->core);
2821 nouveau_bo_unpin_del(&disp->sync);
2823 nouveau_display(dev)->priv = NULL;
2838 return -ENOMEM;
2840 mutex_init(&disp->mutex);
2842 nouveau_display(dev)->priv = disp;
2843 nouveau_display(dev)->dtor = nv50_display_destroy;
2844 nouveau_display(dev)->init = nv50_display_init;
2845 nouveau_display(dev)->fini = nv50_display_fini;
2846 disp->disp = &nouveau_display(dev)->disp;
2847 dev->mode_config.funcs = &nv50_disp_func;
2848 dev->mode_config.helper_private = &nv50_disp_helper_func;
2849 dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true;
2850 dev->mode_config.normalize_zpos = true;
2853 ret = nouveau_bo_new_map(&drm->client, NOUVEAU_GEM_DOMAIN_VRAM, PAGE_SIZE, &disp->sync);
2858 ret = nv50_core_new(drm, &disp->core);
2862 disp->core->func->init(disp->core);
2863 if (disp->core->func->caps_init) {
2864 ret = disp->core->func->caps_init(drm, disp);
2870 if (disp->disp->object.oclass >= TU102_DISP)
2871 nouveau_display(dev)->format_modifiers = wndwc57e_modifiers;
2873 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_FERMI)
2874 nouveau_display(dev)->format_modifiers = disp90xx_modifiers;
2876 nouveau_display(dev)->format_modifiers = disp50xx_modifiers;
2883 * But until then, just limit cursors to 128x128 - which is small enough to avoid ever using
2886 if (disp->disp->object.oclass >= GM107_DISP) {
2887 dev->mode_config.cursor_width = 256;
2888 dev->mode_config.cursor_height = 256;
2889 } else if (disp->disp->object.oclass >= GK104_DISP) {
2890 dev->mode_config.cursor_width = 128;
2891 dev->mode_config.cursor_height = 128;
2893 dev->mode_config.cursor_width = 64;
2894 dev->mode_config.cursor_height = 64;
2898 for_each_set_bit(i, &disp->disp->outp_mask, sizeof(disp->disp->outp_mask) * 8) {
2905 ret = nvif_outp_ctor(disp->disp, "kmsOutp", i, &outp->outp);
2911 connector = nouveau_connector_create(dev, outp->outp.info.conn);
2913 nvif_outp_dtor(&outp->outp);
2918 outp->base.base.possible_crtcs = outp->outp.info.heads;
2919 outp->base.base.possible_clones = 0;
2920 outp->conn = nouveau_connector(connector);
2922 outp->dcb = kzalloc(sizeof(*outp->dcb), GFP_KERNEL);
2923 if (!outp->dcb)
2926 switch (outp->outp.info.proto) {
2928 outp->dcb->type = DCB_OUTPUT_ANALOG;
2929 outp->dcb->crtconf.maxfreq = outp->outp.info.rgb_crt.freq_max;
2932 outp->dcb->type = DCB_OUTPUT_TMDS;
2933 outp->dcb->duallink_possible = outp->outp.info.tmds.dual;
2936 outp->dcb->type = DCB_OUTPUT_LVDS;
2937 outp->dcb->lvdsconf.use_acpi_for_edid = outp->outp.info.lvds.acpi_edid;
2940 outp->dcb->type = DCB_OUTPUT_DP;
2941 outp->dcb->dpconf.link_nr = outp->outp.info.dp.link_nr;
2942 outp->dcb->dpconf.link_bw = outp->outp.info.dp.link_bw;
2943 if (outp->outp.info.dp.mst)
2951 outp->dcb->heads = outp->outp.info.heads;
2952 outp->dcb->connector = outp->outp.info.conn;
2953 outp->dcb->i2c_index = outp->outp.info.ddc;
2955 switch (outp->outp.info.type) {
2966 i, outp->outp.info.type, outp->outp.info.proto, ret);
2971 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2972 if (connector->possible_encoders)
2976 connector->name);
2977 connector->funcs->destroy(connector);
2981 for_each_set_bit(i, &disp->disp->head_mask, sizeof(disp->disp->head_mask) * 8) {
2991 head->msto = nv50_msto_new(dev, head, i);
2992 if (IS_ERR(head->msto)) {
2993 ret = PTR_ERR(head->msto);
2994 head->msto = NULL;
3008 head->msto->encoder.possible_crtcs = disp->disp->head_mask;
3012 /* Disable vblank irqs aggressively for power-saving, safe on nv50+ */
3013 dev->vblank_disable_immediate = true;
3028 * Log2(block height) ----------------------------+ *
3029 * Page Kind ----------------------------------+ | *
3030 * Gob Height/Page Kind Generation ------+ | | *
3031 * Sector layout -------+ | | | *
3032 * Compression ------+ | | | | */
3057 * Log2(block height) ----------------------------+ *
3058 * Page Kind ----------------------------------+ | *
3059 * Gob Height/Page Kind Generation ------+ | | *
3060 * Sector layout -------+ | | | *
3061 * Compression ------+ | | | | */