Lines Matching defs:asyh
380 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
382 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
390 asyh->or.bpc = min_t(u8, asyh->or.bpc, 10);
393 while (asyh->or.bpc > 6) {
394 mode_rate = DIV_ROUND_UP(mode->clock * asyh->or.bpc * 3, 8);
398 asyh->or.bpc -= 2;
413 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
422 asyh->or.bpc = connector->display_info.bpc;
497 struct nv50_head_atom *asyh =
517 core->func->dac->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
518 asyh->or.depth = 0;
972 struct nv50_head_atom *asyh = nv50_head_atom(crtc_state);
992 asyh->or.bpc = connector->display_info.bpc;
993 asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3 << 4);
1006 slots = drm_dp_atomic_find_time_slots(state, &mstm->mgr, mstc->port, asyh->dp.pbn);
1010 asyh->dp.tu = slots;
1031 struct nv50_head_atom *asyh =
1067 mstm->outp->update(mstm->outp, head->base.index, asyh, proto,
1068 nv50_dp_bpc_to_depth(asyh->or.bpc));
1541 struct nv50_head_atom *asyh, u8 proto, u8 depth)
1546 if (!asyh) {
1553 asyh->or.depth = depth;
1556 core->func->sor->ctrl(core, nv_encoder->outp.or.id, nv_encoder->ctrl, asyh);
1609 struct nv50_head *head, struct nv50_head_atom *asyh)
1624 unsigned surfaceWidth = asyh->mode.h.blanks - asyh->mode.h.blanke;
1625 unsigned rasterWidth = asyh->mode.h.active;
1626 unsigned depth = asyh->or.bpc * 3;
1628 u64 pixelClockHz = asyh->mode.clock * 1000;
1748 struct nv50_head_atom *asyh =
1750 struct drm_display_mode *mode = &asyh->state.adjusted_mode;
1822 if (asyh->or.bpc == 8)
1829 nouveau_dp_train(nv_encoder, false, mode->clock, asyh->or.bpc);
1830 nv50_sor_dp_watermark_sst(nv_encoder, head, asyh);
1831 depth = nv50_dp_bpc_to_depth(asyh->or.bpc);
1854 nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);
1985 struct nv50_head_atom *asyh =
1998 switch (asyh->or.bpc) {
1999 case 10: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444; break;
2000 case 8: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444; break;
2001 case 6: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444; break;
2002 default: asyh->or.depth = NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT; break;
2014 nouveau_dp_train(nv_encoder, false, asyh->state.adjusted_mode.clock, 6);
2021 core->func->pior->ctrl(core, nv_encoder->outp.or.id, ctrl, asyh);
2198 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2202 asyh->clr.mask, asyh->set.mask);
2209 if (asyh->clr.mask) {
2210 nv50_head_flush_clr(head, asyh, atom->flush_disable);
2281 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2285 asyh->set.mask, asyh->clr.mask);
2287 if (asyh->set.mask) {
2288 nv50_head_flush_set(head, asyh);
2332 struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);
2336 asyh->set.mask, asyh->clr.mask);
2338 if (asyh->set.mask) {
2339 nv50_head_flush_set_wndw(head, asyh);
2572 struct nv50_head_atom *asyh;
2583 asyh = nv50_head_atom(new_crtc_state);
2584 core->func->head->static_wndw_map(head, asyh);