Lines Matching +full:0 +full:x1200000
54 uint32_t sample = 0;
57 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
58 testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
62 dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
63 head = (dacclk & 0x100) >> 8;
66 gpio1 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC1, 0xff);
67 gpio0 = nvkm_gpio_get(gpio, 0, DCB_GPIO_TVDAC0, 0xff);
72 test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
73 ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
74 ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
75 ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
78 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true);
79 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true);
91 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
93 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
94 (dacclk & ~0xff) | 0x22);
96 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
97 (dacclk & ~0xff) | 0x21);
99 NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
100 NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
102 /* Sample pin 0x4 (usually S-video luma). */
103 NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
105 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
106 & 0x4 << 28;
109 NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
111 sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
112 & 0xa << 28;
115 NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
116 NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
117 NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
118 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
119 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
124 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1);
125 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0);
158 if (drm->client.device.info.chipset == 0x42 ||
159 drm->client.device.info.chipset == 0x43)
161 nv42_tv_sample_load(encoder) >> 28 & 0xe;
164 nv17_dac_sample_load(encoder) >> 28 & 0xe;
168 case 0x2:
169 case 0x4:
172 case 0xc:
175 case 0xe:
206 int n = 0;
253 int i, n = 0;
255 for (i = 0; i < ARRAY_SIZE(modes); i++) {
397 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON);
398 nvkm_gpio_set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON);
440 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
443 dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
446 dacclk |= 0x1a << 16;
449 dacclk |= 0x20;
452 dacclk |= 0x100;
454 dacclk &= ~0x100;
457 dacclk |= 0x10;
461 NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
476 regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
477 regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
478 regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
480 regs->ramdac_8c0 = 0x0;
483 tv_regs->ptv_200 = 0x13111100;
485 tv_regs->ptv_200 |= 0x10;
487 tv_regs->ptv_20c = 0x808010;
488 tv_regs->ptv_304 = 0x2d00000;
489 tv_regs->ptv_600 = 0x0;
490 tv_regs->ptv_60c = 0x0;
491 tv_regs->ptv_610 = 0x1e00000;
494 tv_regs->ptv_508 = 0x1200000;
495 tv_regs->ptv_614 = 0x33;
498 tv_regs->ptv_508 = 0xf00000;
499 tv_regs->ptv_614 = 0x13;
503 tv_regs->ptv_500 = 0xe8e0;
504 tv_regs->ptv_504 = 0x1710;
505 tv_regs->ptv_604 = 0x0;
506 tv_regs->ptv_608 = 0x0;
509 tv_regs->ptv_604 = 0x20;
510 tv_regs->ptv_608 = 0x10;
511 tv_regs->ptv_500 = 0x19710;
512 tv_regs->ptv_504 = 0x68f0;
515 tv_regs->ptv_604 = 0x10;
516 tv_regs->ptv_608 = 0x20;
517 tv_regs->ptv_500 = 0x4b90;
518 tv_regs->ptv_504 = 0x1b480;
522 for (i = 0; i < 0x40; i++)
529 /* The registers in PRAMDAC+0xc00 control some timings and CSC
537 for (i = 0; i < 38; i++)
572 regs->fp_debug_2 = 0;
574 regs->fp_margin_color = 0x801080;
597 if (drm->client.device.info.chipset < 0x44)
598 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
600 0xf0000000);
602 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
604 0x00100000);
619 NVReadRAMDAC(dev, 0,
632 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
656 if (i < 0)
687 return 0;
752 drm_helper_probe_single_connector_modes(connector, 0, 0);
762 return 0;
807 tv_enc->hue = 0;
811 tv_enc->pin_mask = 0;
827 encoder->possible_clones = 0;
831 return 0;