Lines Matching refs:head
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaSeq() argument
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVWriteVgaSeq()
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); in NVWriteVgaSeq()
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) in NVReadVgaSeq() argument
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); in NVReadVgaSeq()
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); in NVReadVgaSeq()
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) in NVWriteVgaGr() argument
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVWriteVgaGr()
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); in NVWriteVgaGr()
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) in NVReadVgaGr() argument
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); in NVReadVgaGr()
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); in NVReadVgaGr()
110 NVBlankScreen(struct drm_device *dev, int head, bool blank) in NVBlankScreen() argument
115 NVSetOwner(dev, head); in NVBlankScreen()
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); in NVBlankScreen()
119 NVVgaSeqReset(dev, head, true); in NVBlankScreen()
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); in NVBlankScreen()
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); in NVBlankScreen()
124 NVVgaSeqReset(dev, head, false); in NVBlankScreen()
252 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) in nouveau_hw_fix_bad_vpll() argument
265 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; in nouveau_hw_fix_bad_vpll()
276 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); in nouveau_hw_fix_bad_vpll()
379 rd_cio_state(struct drm_device *dev, int head, in rd_cio_state() argument
382 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); in rd_cio_state()
386 wr_cio_state(struct drm_device *dev, int head, in wr_cio_state() argument
389 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); in wr_cio_state()
393 nv_save_state_ramdac(struct drm_device *dev, int head, in nv_save_state_ramdac() argument
397 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ramdac()
401 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); in nv_save_state_ramdac()
403 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); in nv_save_state_ramdac()
408 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); in nv_save_state_ramdac()
410 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); in nv_save_state_ramdac()
413 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); in nv_save_state_ramdac()
415 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); in nv_save_state_ramdac()
417 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); in nv_save_state_ramdac()
418 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); in nv_save_state_ramdac()
419 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); in nv_save_state_ramdac()
420 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); in nv_save_state_ramdac()
421 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); in nv_save_state_ramdac()
422 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); in nv_save_state_ramdac()
423 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); in nv_save_state_ramdac()
424 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); in nv_save_state_ramdac()
428 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); in nv_save_state_ramdac()
429 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); in nv_save_state_ramdac()
433 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); in nv_save_state_ramdac()
435 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); in nv_save_state_ramdac()
436 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); in nv_save_state_ramdac()
440 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); in nv_save_state_ramdac()
441 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); in nv_save_state_ramdac()
442 if (!nv_gf4_disp_arch(dev) && head == 0) { in nv_save_state_ramdac()
448 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); in nv_save_state_ramdac()
449 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); in nv_save_state_ramdac()
451 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); in nv_save_state_ramdac()
454 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); in nv_save_state_ramdac()
457 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); in nv_save_state_ramdac()
458 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); in nv_save_state_ramdac()
459 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); in nv_save_state_ramdac()
462 regp->ctv_regs[i] = NVReadRAMDAC(dev, head, in nv_save_state_ramdac()
468 nv_load_state_ramdac(struct drm_device *dev, int head, in nv_load_state_ramdac() argument
473 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ramdac()
474 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; in nv_load_state_ramdac()
478 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); in nv_load_state_ramdac()
485 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); in nv_load_state_ramdac()
487 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); in nv_load_state_ramdac()
490 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); in nv_load_state_ramdac()
492 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); in nv_load_state_ramdac()
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); in nv_load_state_ramdac()
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); in nv_load_state_ramdac()
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); in nv_load_state_ramdac()
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); in nv_load_state_ramdac()
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); in nv_load_state_ramdac()
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); in nv_load_state_ramdac()
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); in nv_load_state_ramdac()
501 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); in nv_load_state_ramdac()
506 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); in nv_load_state_ramdac()
507 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); in nv_load_state_ramdac()
511 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); in nv_load_state_ramdac()
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); in nv_load_state_ramdac()
514 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); in nv_load_state_ramdac()
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); in nv_load_state_ramdac()
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); in nv_load_state_ramdac()
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); in nv_load_state_ramdac()
521 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); in nv_load_state_ramdac()
523 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); in nv_load_state_ramdac()
526 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); in nv_load_state_ramdac()
529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); in nv_load_state_ramdac()
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); in nv_load_state_ramdac()
531 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); in nv_load_state_ramdac()
534 NVWriteRAMDAC(dev, head, in nv_load_state_ramdac()
540 nv_save_state_vga(struct drm_device *dev, int head, in nv_save_state_vga() argument
543 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_vga()
546 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); in nv_save_state_vga()
549 rd_cio_state(dev, head, regp, i); in nv_save_state_vga()
551 NVSetEnablePalette(dev, head, true); in nv_save_state_vga()
553 regp->Attribute[i] = NVReadVgaAttr(dev, head, i); in nv_save_state_vga()
554 NVSetEnablePalette(dev, head, false); in nv_save_state_vga()
557 regp->Graphics[i] = NVReadVgaGr(dev, head, i); in nv_save_state_vga()
560 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); in nv_save_state_vga()
564 nv_load_state_vga(struct drm_device *dev, int head, in nv_load_state_vga() argument
567 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_vga()
570 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); in nv_load_state_vga()
573 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); in nv_load_state_vga()
575 nv_lock_vga_crtc_base(dev, head, false); in nv_load_state_vga()
577 wr_cio_state(dev, head, regp, i); in nv_load_state_vga()
578 nv_lock_vga_crtc_base(dev, head, true); in nv_load_state_vga()
581 NVWriteVgaGr(dev, head, i, regp->Graphics[i]); in nv_load_state_vga()
583 NVSetEnablePalette(dev, head, true); in nv_load_state_vga()
585 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); in nv_load_state_vga()
586 NVSetEnablePalette(dev, head, false); in nv_load_state_vga()
590 nv_save_state_ext(struct drm_device *dev, int head, in nv_save_state_ext() argument
594 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_save_state_ext()
597 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_save_state_ext()
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_save_state_ext()
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_save_state_ext()
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_save_state_ext()
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_save_state_ext()
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_save_state_ext()
603 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_save_state_ext()
605 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_save_state_ext()
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_save_state_ext()
607 rd_cio_state(dev, head, regp, NV_CIO_CRE_21); in nv_save_state_ext()
610 rd_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_save_state_ext()
613 rd_cio_state(dev, head, regp, 0x9f); in nv_save_state_ext()
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_save_state_ext()
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_save_state_ext()
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_save_state_ext()
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_save_state_ext()
619 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_save_state_ext()
622 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); in nv_save_state_ext()
623 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); in nv_save_state_ext()
626 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); in nv_save_state_ext()
629 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); in nv_save_state_ext()
632 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); in nv_save_state_ext()
633 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); in nv_save_state_ext()
636 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); in nv_save_state_ext()
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_save_state_ext()
639 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_save_state_ext()
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_save_state_ext()
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_save_state_ext()
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_save_state_ext()
644 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_save_state_ext()
648 rd_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_save_state_ext()
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_save_state_ext()
650 rd_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_save_state_ext()
653 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); in nv_save_state_ext()
654 rd_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_save_state_ext()
655 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_save_state_ext()
657 rd_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_save_state_ext()
658 rd_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_save_state_ext()
661 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); in nv_save_state_ext()
665 nv_load_state_ext(struct drm_device *dev, int head, in nv_load_state_ext() argument
670 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; in nv_load_state_ext()
680 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); in nv_load_state_ext()
692 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); in nv_load_state_ext()
693 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); in nv_load_state_ext()
694 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); in nv_load_state_ext()
697 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); in nv_load_state_ext()
700 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); in nv_load_state_ext()
702 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); in nv_load_state_ext()
704 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); in nv_load_state_ext()
706 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_load_state_ext()
710 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); in nv_load_state_ext()
712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); in nv_load_state_ext()
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); in nv_load_state_ext()
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); in nv_load_state_ext()
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); in nv_load_state_ext()
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); in nv_load_state_ext()
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); in nv_load_state_ext()
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); in nv_load_state_ext()
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); in nv_load_state_ext()
720 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); in nv_load_state_ext()
723 wr_cio_state(dev, head, regp, NV_CIO_CRE_47); in nv_load_state_ext()
726 wr_cio_state(dev, head, regp, 0x9f); in nv_load_state_ext()
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_49); in nv_load_state_ext()
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); in nv_load_state_ext()
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); in nv_load_state_ext()
731 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); in nv_load_state_ext()
733 nv_fix_nv40_hw_cursor(dev, head); in nv_load_state_ext()
734 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); in nv_load_state_ext()
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); in nv_load_state_ext()
737 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); in nv_load_state_ext()
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); in nv_load_state_ext()
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); in nv_load_state_ext()
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); in nv_load_state_ext()
742 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); in nv_load_state_ext()
759 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); in nv_load_state_ext()
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); in nv_load_state_ext()
761 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); in nv_load_state_ext()
764 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); in nv_load_state_ext()
765 wr_cio_state(dev, head, regp, NV_CIO_CRE_59); in nv_load_state_ext()
766 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); in nv_load_state_ext()
768 wr_cio_state(dev, head, regp, NV_CIO_CRE_85); in nv_load_state_ext()
769 wr_cio_state(dev, head, regp, NV_CIO_CRE_86); in nv_load_state_ext()
772 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); in nv_load_state_ext()
776 nv_save_state_palette(struct drm_device *dev, int head, in nv_save_state_palette() argument
780 int head_offset = head * NV_PRMDIO_SIZE, i; in nv_save_state_palette()
787 state->crtc_reg[head].DAC[i] = nvif_rd08(device, in nv_save_state_palette()
791 NVSetEnablePalette(dev, head, false); in nv_save_state_palette()
795 nouveau_hw_load_state_palette(struct drm_device *dev, int head, in nouveau_hw_load_state_palette() argument
799 int head_offset = head * NV_PRMDIO_SIZE, i; in nouveau_hw_load_state_palette()
807 state->crtc_reg[head].DAC[i]); in nouveau_hw_load_state_palette()
810 NVSetEnablePalette(dev, head, false); in nouveau_hw_load_state_palette()
813 void nouveau_hw_save_state(struct drm_device *dev, int head, in nouveau_hw_save_state() argument
820 nouveau_hw_fix_bad_vpll(dev, head); in nouveau_hw_save_state()
821 nv_save_state_ramdac(dev, head, state); in nouveau_hw_save_state()
822 nv_save_state_vga(dev, head, state); in nouveau_hw_save_state()
823 nv_save_state_palette(dev, head, state); in nouveau_hw_save_state()
824 nv_save_state_ext(dev, head, state); in nouveau_hw_save_state()
827 void nouveau_hw_load_state(struct drm_device *dev, int head, in nouveau_hw_load_state() argument
830 NVVgaProtect(dev, head, true); in nouveau_hw_load_state()
831 nv_load_state_ramdac(dev, head, state); in nouveau_hw_load_state()
832 nv_load_state_ext(dev, head, state); in nouveau_hw_load_state()
833 nouveau_hw_load_state_palette(dev, head, state); in nouveau_hw_load_state()
834 nv_load_state_vga(dev, head, state); in nouveau_hw_load_state()
835 NVVgaProtect(dev, head, false); in nouveau_hw_load_state()