Lines Matching +full:spread +full:- +full:spectrum
5 * Copyright 2007-2009 Stuart Bennett
58 * this does not give a correct answer for off-chip dvi, but there's no
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
72 * Luckily we do know the values ;-)
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2;
84 if (dcbent->type == DCB_OUTPUT_LVDS)
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04);
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08);
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
115 struct drm_device *dev = encoder->dev;
121 nv_crtc = nouveau_crtc(encoder->crtc);
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
129 *fpc = nv_crtc->dpms_saved_fp_control;
132 nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index;
133 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc);
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control;
139 nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index);
140 if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) {
141 nv_crtc->dpms_saved_fp_control = *fpc;
145 NVWriteRAMDAC(dev, nv_crtc->index,
154 struct drm_device *dev = encoder->dev;
155 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
158 if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP)
164 * always hard-wired to a reasonable configuration using straps,
171 list_for_each_entry(slave, &dev->mode_config.encoder_list, head) {
172 struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb;
174 if (slave_dcb->type == DCB_OUTPUT_TMDS && get_encoder_i2c_funcs(slave) &&
175 slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr)
190 if (!nv_connector->native_mode ||
191 nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
192 mode->hdisplay > nv_connector->native_mode->hdisplay ||
193 mode->vdisplay > nv_connector->native_mode->vdisplay) {
194 nv_encoder->mode = *adjusted_mode;
197 nv_encoder->mode = *nv_connector->native_mode;
198 adjusted_mode->clock = nv_connector->native_mode->clock;
207 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
208 uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000;
210 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP)
214 * It toggles spread spectrum PLL output and sets the bindings of PLLs
218 state->sel_clk |= bits1618;
220 state->sel_clk &= ~bits1618;
223 * bit 0 NVClk spread spectrum on/off
224 * bit 2 MemClk spread spectrum on/off
225 * bit 4 PixClk1 spread spectrum on/off toggle
226 * bit 6 PixClk2 spread spectrum on/off toggle
231 * maybe a different spread mode
232 * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts)
233 * The logic behind turning spread spectrum on/off in the first place,
234 * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table
237 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) {
238 int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1;
240 state->sel_clk &= ~0xf0;
241 state->sel_clk |= (head ? 0x40 : 0x10) << shift;
248 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
249 struct drm_device *dev = encoder->dev;
250 int head = nouveau_crtc(encoder->crtc)->index;
251 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg;
255 helper->dpms(encoder, DRM_MODE_DPMS_OFF);
262 if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP)
265 *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30;
266 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
284 struct drm_device *dev = encoder->dev;
285 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
287 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
288 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
289 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
292 struct drm_display_mode *output_mode = &nv_encoder->mode;
293 struct drm_connector *connector = &nv_connector->base;
294 const struct drm_framebuffer *fb = encoder->crtc->primary->fb;
297 NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index);
301 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
302 regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
304 (output_mode->hsync_start - output_mode->hdisplay) >=
305 drm->vbios.digital_min_front_porch)
306 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay;
308 regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1;
309 regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1;
310 regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
311 regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew;
312 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1;
314 regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
315 regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
316 regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1;
317 regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1;
318 regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
319 regp->fp_vert_regs[FP_VALID_START] = 0;
320 regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1;
323 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
324 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG));
327 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
328 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
329 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
330 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
332 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE ||
333 nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */
334 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER;
335 else if (adjusted_mode->hdisplay == output_mode->hdisplay &&
336 adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE;
339 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE;
341 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
342 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP &&
343 output_mode->clock > 165000)
344 regp->fp_control |= (2 << 24);
345 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
347 if (nv_connector->edid &&
348 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
349 duallink = (((u8 *)nv_connector->edid)[121] == 2);
351 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
356 regp->fp_control |= (8 << 28);
358 if (output_mode->clock > 165000)
359 regp->fp_control |= (8 << 28);
361 regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
370 regp->fp_debug_1 = 0;
372 regp->fp_debug_2 = 0;
375 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay;
376 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay;
379 if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT &&
389 scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay;
390 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE |
394 diff = output_mode->hdisplay -
395 output_mode->vdisplay * mode_ratio / (1 << 12);
396 regp->fp_horiz_regs[FP_VALID_START] += diff / 2;
397 regp->fp_horiz_regs[FP_VALID_END] -= diff / 2;
405 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay;
406 regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE |
410 diff = output_mode->vdisplay -
411 (1 << 12) * output_mode->hdisplay / mode_ratio;
412 regp->fp_vert_regs[FP_VALID_START] += diff / 2;
413 regp->fp_vert_regs[FP_VALID_END] -= diff / 2;
418 if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
419 (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
420 fb->format->depth > connector->display_info.bpc * 3)) {
421 if (drm->client.device.info.chipset == 0x11)
422 regp->dither = savep->dither | 0x00010000;
425 regp->dither = savep->dither | 0x00000001;
427 regp->dither_regs[i] = 0xe4e4e4e4;
428 regp->dither_regs[i + 3] = 0x44444444;
432 if (drm->client.device.info.chipset != 0x11) {
436 regp->dither_regs[i] = savep->dither_regs[i];
437 regp->dither_regs[i + 3] = savep->dither_regs[i + 3];
440 regp->dither = savep->dither;
443 regp->fp_margin_color = 0;
448 struct drm_device *dev = encoder->dev;
450 const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
451 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
453 struct dcb_output *dcbe = nv_encoder->dcb;
454 int head = nouveau_crtc(encoder->crtc)->index;
457 if (dcbe->type == DCB_OUTPUT_TMDS)
458 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
459 else if (dcbe->type == DCB_OUTPUT_LVDS)
460 call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock);
464 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control =
468 if (drm->client.device.info.chipset < 0x44)
476 get_encoder_i2c_funcs(slave_encoder)->mode_set(slave_encoder,
477 &nv_encoder->mode,
478 &nv_encoder->mode);
480 helper->dpms(encoder, DRM_MODE_DPMS_ON);
483 nv04_encoder_get_connector(nv_encoder)->base.name,
484 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
490 struct drm_device *dev = encoder->dev;
491 struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
492 struct pci_dev *pdev = to_pci_dev(dev->dev);
497 if (pdev->device == 0x0174 || pdev->device == 0x0179 ||
498 pdev->device == 0x0189 || pdev->device == 0x0329) {
517 struct drm_device *dev = encoder->dev;
518 struct drm_crtc *crtc = encoder->crtc;
521 bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms);
523 if (nv_encoder->last_dpms == mode)
525 nv_encoder->last_dpms = mode;
528 mode, nv_encoder->dcb->index);
533 if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
537 int head = crtc ? nouveau_crtc(crtc)->index :
538 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
541 call_lvds_script(dev, nv_encoder->dcb, head,
542 LVDS_PANEL_ON, nv_encoder->mode.clock);
547 call_lvds_script(dev, nv_encoder->dcb, head,
555 nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index);
557 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
558 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0;
560 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
565 struct nouveau_drm *drm = nouveau_drm(encoder->dev);
568 if (nv_encoder->last_dpms == mode)
570 nv_encoder->last_dpms = mode;
573 mode, nv_encoder->dcb->index);
582 struct drm_device *dev = encoder->dev;
585 nv_encoder->restore.head =
586 nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
592 struct drm_device *dev = encoder->dev;
593 int head = nv_encoder->restore.head;
595 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) {
599 if (connector && connector->native_mode)
600 call_lvds_script(dev, nv_encoder->dcb, head,
602 connector->native_mode->clock);
604 } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) {
606 (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals);
608 run_tmds_table(dev, nv_encoder->dcb, head, clock);
611 nv_encoder->last_dpms = NV_DPMS_CLEARED;
619 get_encoder_i2c_funcs(encoder)->destroy(encoder);
627 struct drm_device *dev = encoder->dev;
628 struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
636 .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38),
654 &bus->i2c, &info[type].dev);
687 switch (entry->type) {
697 return -EINVAL;
702 return -ENOMEM;
704 nv_encoder->enc_save = nv04_dfp_save;
705 nv_encoder->enc_restore = nv04_dfp_restore;
709 nv_encoder->dcb = entry;
710 nv_encoder->or = ffs(entry->or) - 1;
712 drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type, NULL);
715 encoder->possible_crtcs = entry->heads;
716 encoder->possible_clones = 0;
718 if (entry->type == DCB_OUTPUT_TMDS &&
719 entry->location != DCB_LOC_ON_CHIP)