Lines Matching +full:0 +full:x4038
71 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
85 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ in nv_crtc_set_image_sharpening()
86 level += 0x40; in nv_crtc_set_image_sharpening()
103 /* NV4x 0x40.. pll notes:
104 * gpu pll: 0x4000 + 0x4004
105 * ?gpu? pll: 0x4008 + 0x400c
106 * vpll1: 0x4010 + 0x4014
107 * vpll2: 0x4018 + 0x401c
108 * mpll: 0x4020 + 0x4024
109 * mpll: 0x4038 + 0x403c
112 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
133 /* NM2 == 0 is used to determine single stage mode on two stage plls */ in nv_crtc_calc_state_ext()
134 pv->NM2 = 0; in nv_crtc_calc_state_ext()
141 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, in nv_crtc_calc_state_ext()
146 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) in nv_crtc_calc_state_ext()
147 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); in nv_crtc_calc_state_ext()
159 if (drm->client.device.info.chipset < 0x41) in nv_crtc_calc_state_ext()
180 unsigned char seq1 = 0, crtc17 = 0; in nv_crtc_dpms()
196 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; in nv_crtc_dpms()
200 seq1 = 0x20; in nv_crtc_dpms()
201 crtc17 = 0x80; in nv_crtc_dpms()
202 crtc1A |= 0x80; in nv_crtc_dpms()
206 seq1 = 0x20; in nv_crtc_dpms()
207 crtc17 = 0x80; in nv_crtc_dpms()
208 crtc1A |= 0x40; in nv_crtc_dpms()
212 seq1 = 0x20; in nv_crtc_dpms()
213 crtc17 = 0x00; in nv_crtc_dpms()
214 crtc1A |= 0xC0; in nv_crtc_dpms()
219 seq1 = 0x00; in nv_crtc_dpms()
220 crtc17 = 0x80; in nv_crtc_dpms()
226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); in nv_crtc_dpms()
228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); in nv_crtc_dpms()
277 #if 0 in nv_crtc_mode_set_vga()
287 #if 0 in nv_crtc_mode_set_vga()
288 ErrorF("horizDisplay: 0x%X \n", horizDisplay); in nv_crtc_mode_set_vga()
289 ErrorF("horizStart: 0x%X \n", horizStart); in nv_crtc_mode_set_vga()
290 ErrorF("horizEnd: 0x%X \n", horizEnd); in nv_crtc_mode_set_vga()
291 ErrorF("horizTotal: 0x%X \n", horizTotal); in nv_crtc_mode_set_vga()
292 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); in nv_crtc_mode_set_vga()
293 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); in nv_crtc_mode_set_vga()
294 ErrorF("vertDisplay: 0x%X \n", vertDisplay); in nv_crtc_mode_set_vga()
295 ErrorF("vertStart: 0x%X \n", vertStart); in nv_crtc_mode_set_vga()
296 ErrorF("vertEnd: 0x%X \n", vertEnd); in nv_crtc_mode_set_vga()
297 ErrorF("vertTotal: 0x%X \n", vertTotal); in nv_crtc_mode_set_vga()
298 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); in nv_crtc_mode_set_vga()
299 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); in nv_crtc_mode_set_vga()
308 regp->MiscOutReg = 0x23; in nv_crtc_mode_set_vga()
310 regp->MiscOutReg |= 0x40; in nv_crtc_mode_set_vga()
312 regp->MiscOutReg |= 0x80; in nv_crtc_mode_set_vga()
320 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ in nv_crtc_mode_set_vga()
322 regp->MiscOutReg = 0x63; /* -hsync +vsync */ in nv_crtc_mode_set_vga()
324 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ in nv_crtc_mode_set_vga()
326 regp->MiscOutReg = 0x23; /* +hsync +vsync */ in nv_crtc_mode_set_vga()
332 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; in nv_crtc_mode_set_vga()
333 /* 0x20 disables the sequencer */ in nv_crtc_mode_set_vga()
335 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; in nv_crtc_mode_set_vga()
337 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; in nv_crtc_mode_set_vga()
338 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; in nv_crtc_mode_set_vga()
339 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
340 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; in nv_crtc_mode_set_vga()
349 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); in nv_crtc_mode_set_vga()
352 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); in nv_crtc_mode_set_vga()
362 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
363 …CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | in nv_crtc_mode_set_vga()
366 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; in nv_crtc_mode_set_vga()
367 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; in nv_crtc_mode_set_vga()
368 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
369 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
370 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
371 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
373 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); in nv_crtc_mode_set_vga()
376 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; in nv_crtc_mode_set_vga()
377 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; in nv_crtc_mode_set_vga()
380 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; in nv_crtc_mode_set_vga()
381 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; in nv_crtc_mode_set_vga()
389 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); in nv_crtc_mode_set_vga()
391 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); in nv_crtc_mode_set_vga()
393 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; in nv_crtc_mode_set_vga()
413 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ in nv_crtc_mode_set_vga()
418 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; in nv_crtc_mode_set_vga()
419 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; in nv_crtc_mode_set_vga()
420 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
421 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
422 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ in nv_crtc_mode_set_vga()
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ in nv_crtc_mode_set_vga()
425 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; in nv_crtc_mode_set_vga()
426 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; in nv_crtc_mode_set_vga()
428 regp->Attribute[0] = 0x00; /* standard colormap translation */ in nv_crtc_mode_set_vga()
429 regp->Attribute[1] = 0x01; in nv_crtc_mode_set_vga()
430 regp->Attribute[2] = 0x02; in nv_crtc_mode_set_vga()
431 regp->Attribute[3] = 0x03; in nv_crtc_mode_set_vga()
432 regp->Attribute[4] = 0x04; in nv_crtc_mode_set_vga()
433 regp->Attribute[5] = 0x05; in nv_crtc_mode_set_vga()
434 regp->Attribute[6] = 0x06; in nv_crtc_mode_set_vga()
435 regp->Attribute[7] = 0x07; in nv_crtc_mode_set_vga()
436 regp->Attribute[8] = 0x08; in nv_crtc_mode_set_vga()
437 regp->Attribute[9] = 0x09; in nv_crtc_mode_set_vga()
438 regp->Attribute[10] = 0x0A; in nv_crtc_mode_set_vga()
439 regp->Attribute[11] = 0x0B; in nv_crtc_mode_set_vga()
440 regp->Attribute[12] = 0x0C; in nv_crtc_mode_set_vga()
441 regp->Attribute[13] = 0x0D; in nv_crtc_mode_set_vga()
442 regp->Attribute[14] = 0x0E; in nv_crtc_mode_set_vga()
443 regp->Attribute[15] = 0x0F; in nv_crtc_mode_set_vga()
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ in nv_crtc_mode_set_vga()
446 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; in nv_crtc_mode_set_vga()
447 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ in nv_crtc_mode_set_vga()
448 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; in nv_crtc_mode_set_vga()
449 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
493 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ in nv_crtc_mode_set_regs()
496 regp->crtc_eng_ctrl = 0; in nv_crtc_mode_set_regs()
498 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
500 #if 0 in nv_crtc_mode_set_regs()
513 if (drm->client.device.info.chipset >= 0x11) in nv_crtc_mode_set_regs()
519 regp->CRTC[NV_CIO_CRE_53] = 0; in nv_crtc_mode_set_regs()
520 regp->CRTC[NV_CIO_CRE_54] = 0; in nv_crtc_mode_set_regs()
522 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ in nv_crtc_mode_set_regs()
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; in nv_crtc_mode_set_regs()
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; in nv_crtc_mode_set_regs()
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; in nv_crtc_mode_set_regs()
541 if (nv_crtc->index == 0) in nv_crtc_mode_set_regs()
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; in nv_crtc_mode_set_regs()
544 /* The blob seems to take the current value from crtc 0, add 4 to that in nv_crtc_mode_set_regs()
546 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()
550 /* the blob sometimes sets |= 0x10 (which is the same as setting |= in nv_crtc_mode_set_regs()
551 * 1 << 30 on 0x60.830), for no apparent reason */ in nv_crtc_mode_set_regs()
555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; in nv_crtc_mode_set_regs()
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); in nv_crtc_mode_set_regs()
565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); in nv_crtc_mode_set_regs()
574 regp->CRTC[NV_CIO_CRE_85] = 0xFF; in nv_crtc_mode_set_regs()
575 regp->CRTC[NV_CIO_CRE_86] = 0x1; in nv_crtc_mode_set_regs()
594 if (drm->client.device.info.chipset >= 0x11) in nv_crtc_mode_set_regs()
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ in nv_crtc_mode_set_regs()
598 regp->tv_setup = 0; in nv_crtc_mode_set_regs()
603 regp->ramdac_8c0 = 0x100; in nv_crtc_mode_set_regs()
604 regp->ramdac_a20 = 0x0; in nv_crtc_mode_set_regs()
605 regp->ramdac_a24 = 0xfffff; in nv_crtc_mode_set_regs()
606 regp->ramdac_a34 = 0x1; in nv_crtc_mode_set_regs()
614 struct nouveau_bo *nvbo = nouveau_gem_object(fb->obj[0]); in nv_crtc_swap_fbs()
619 if (ret == 0) { in nv_crtc_swap_fbs()
665 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()
668 return 0; in nv_crtc_mode_set()
686 state->sel_clk = saved->sel_clk & ~(0x5 << 16); in nv_crtc_save()
727 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); in nv_crtc_prepare()
793 for (i = 0; i < 256; i++) { in nv_crtc_gamma_load()
826 * mark the lut values as dirty by setting depth==0, and it'll be in nv_crtc_gamma_set()
830 nv_crtc->lut.depth = 0; in nv_crtc_gamma_set()
831 return 0; in nv_crtc_gamma_set()
836 return 0; in nv_crtc_gamma_set()
857 return 0; in nv04_crtc_do_mode_set_base()
869 nvbo = nouveau_gem_object(drm_fb->obj[0]); in nv04_crtc_do_mode_set_base()
887 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; in nv04_crtc_do_mode_set_base()
889 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); in nv04_crtc_do_mode_set_base()
891 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); in nv04_crtc_do_mode_set_base()
898 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); in nv04_crtc_do_mode_set_base()
902 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, in nv04_crtc_do_mode_set_base()
906 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; in nv04_crtc_do_mode_set_base()
915 return 0; in nv04_crtc_do_mode_set_base()
943 for (i = 0; i < width; i++) { in nv04_cursor_upload()
944 for (j = 0; j < width; j++) { in nv04_cursor_upload()
947 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 in nv04_cursor_upload()
948 | (pixel & 0xf80000) >> 9 in nv04_cursor_upload()
949 | (pixel & 0xf800) >> 6 in nv04_cursor_upload()
950 | (pixel & 0xf8) >> 3); in nv04_cursor_upload()
967 for (i = 0; i < 64 * 64; i++) { in nv11_cursor_upload()
976 if (alpha > 0 && alpha < 255) in nv11_cursor_upload()
977 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); in nv11_cursor_upload()
983 if (drm->client.device.info.chipset == 0x11) { in nv11_cursor_upload()
984 pixel = ((pixel & 0x000000ff) << 24) | in nv11_cursor_upload()
985 ((pixel & 0x0000ff00) << 8) | in nv11_cursor_upload()
986 ((pixel & 0x00ff0000) >> 8) | in nv11_cursor_upload()
987 ((pixel & 0xff000000) >> 24); in nv11_cursor_upload()
1005 int ret = 0; in nv04_crtc_cursor_set()
1009 return 0; in nv04_crtc_cursor_set()
1024 if (drm->client.device.info.chipset >= 0x11) in nv04_crtc_cursor_set()
1044 return 0; in nv04_crtc_cursor_move()
1087 return 0; in nv04_finish_page_flip()
1137 PUSH_NVSQ(push, NV_SW, NV_SW_PAGE_FLIP, 0x00000000); in nv04_page_flip_emit()
1144 return 0; in nv04_page_flip_emit()
1157 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; in nv04_crtc_page_flip()
1161 struct nouveau_bo *old_bo = nouveau_gem_object(old_fb->obj[0]); in nv04_crtc_page_flip()
1162 struct nouveau_bo *new_bo = nouveau_gem_object(fb->obj[0]); in nv04_crtc_page_flip()
1210 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], in nv04_crtc_page_flip()
1222 PUSH_NVSQ(push, NV05F, 0x012c, 0); in nv04_crtc_page_flip()
1223 PUSH_NVSQ(push, NV05F, 0x0134, head); in nv04_crtc_page_flip()
1224 PUSH_NVSQ(push, NV05F, 0x0100, 0); in nv04_crtc_page_flip()
1225 PUSH_NVSQ(push, NV05F, 0x0130, 0); in nv04_crtc_page_flip()
1247 return 0; in nv04_crtc_page_flip()
1315 nv_crtc->lut.depth = 0; in nv04_crtc_create()
1323 primary = __drm_universal_plane_alloc(dev, sizeof(*primary), 0, 0, in nv04_crtc_create()
1339 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, in nv04_crtc_create()
1340 NOUVEAU_GEM_DOMAIN_VRAM, 0, 0x0000, NULL, NULL, in nv04_crtc_create()