2  * Copyright 1993-2003 NVIDIA, Corporation
3  * Copyright 2007-2009 Stuart Bennett
38 	int burst;  member
63 	pclk_freq = arb->pclk_khz;  in nv04_calc_arb()
64 	mclk_freq = arb->mclk_khz;  in nv04_calc_arb()
65 	nvclk_freq = arb->nvclk_khz;  in nv04_calc_arb()
66 	pagemiss = arb->mem_page_miss;  in nv04_calc_arb()
67 	cas = arb->mem_latency;  in nv04_calc_arb()
68 	bpp = arb->bpp;  in nv04_calc_arb()
92 		m1 = clwm + cbs - 512;  in nv04_calc_arb()
97 			mclk_extra--;  in nv04_calc_arb()
102 		fifo->lwm = clwm;  in nv04_calc_arb()
103 		fifo->burst = cbs;  in nv04_calc_arb()
117 				   * to the CRTC FIFO burst. (ns) */  in nv10_calc_arb()
119 	pclk_freq = arb->pclk_khz;  in nv10_calc_arb()
120 	nvclk_freq = arb->nvclk_khz;  in nv10_calc_arb()
121 	mclk_freq = arb->mclk_khz;  in nv10_calc_arb()
123 	fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */  in nv10_calc_arb()
124 	drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */  in nv10_calc_arb()
126 	fifo_len = arb->two_heads ? 1536 : 1024; /* B */  in nv10_calc_arb()
128 	/* Fixed FIFO refill latency. */  in nv10_calc_arb()
132 	nvclks = 3	/* lwm -> sync. */  in nv10_calc_arb()
149 	mclks += (arb->memory_type == 0 ? 2 : 1)  in nv10_calc_arb()
150 		* arb->memory_width / 32;  in nv10_calc_arb()
158 	xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to  in nv10_calc_arb()
160 		+ 2 * arb->mem_page_miss       /* Extra pagemiss latency. */  in nv10_calc_arb()
161 		+ (arb->bpp == 32 ? 8 : 4);    /* Margin of error. */  in nv10_calc_arb()
165 	if (arb->two_heads)  in nv10_calc_arb()
169 	/* FIFO burst */  in nv10_calc_arb()
171 	/* Max burst not leading to overflows. */  in nv10_calc_arb()
172 	max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000))  in nv10_calc_arb()
173 		* (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000);  in nv10_calc_arb()
174 	fifo->burst = min(max_burst_o, 1024);  in nv10_calc_arb()
176 	/* Max burst value with an acceptable latency. */  in nv10_calc_arb()
178 	fifo->burst = min(max_burst_l, fifo->burst);  in nv10_calc_arb()
180 	fifo->burst = rounddown_pow_of_two(fifo->burst);  in nv10_calc_arb()
185 	max_lwm = fifo_len - fifo->burst  in nv10_calc_arb()
187 		+ fifo->burst * drain_rate / fill_rate;  in nv10_calc_arb()
189 	fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */  in nv10_calc_arb()
194 		int *burst, int *lwm)  in nv04_update_arb()  argument
197 	struct nvif_object *device = &nouveau_drm(dev)->client.device.object;  in nv04_update_arb()
203 	struct pci_dev *pdev = to_pci_dev(dev->dev);  in nv04_update_arb()
210 	if ((pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||  in nv04_update_arb()
211 	    (pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {  in nv04_update_arb()
213 		int domain = pci_domain_nr(pdev->bus);  in nv04_update_arb()
229 	if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT)  in nv04_update_arb()
234 	*burst = ilog2(fifo_data.burst >> 4);  in nv04_update_arb()
239 nv20_update_arb(int *burst, int *lwm)  in nv20_update_arb()  argument
245 	graphics_lwm = fifo_size - burst_size;  in nv20_update_arb()
247 	*burst = ilog2(burst_size >> 5);  in nv20_update_arb()
252 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm)  in nouveau_calc_arb()  argument
255 	struct pci_dev *pdev = to_pci_dev(dev->dev);  in nouveau_calc_arb()
257 	if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN)  in nouveau_calc_arb()
258 		nv04_update_arb(dev, vclk, bpp, burst, lwm);  in nouveau_calc_arb()
259 	else if ((pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||  in nouveau_calc_arb()
260 		 (pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {  in nouveau_calc_arb()
261 		*burst = 128;  in nouveau_calc_arb()
264 		nv20_update_arb(burst, lwm);  in nouveau_calc_arb()