Lines Matching +full:0 +full:x88000
11 <value name="VG1" value="0"/>
21 <value name="MIXER0" value="0"/>
30 LCDC_RGB_INTF, /* 0 */
31 DTV_INTF = LCDC_RGB_INTF, /* 0 */
44 <value name="INTF_LCDC_DTV" value="0"/> <!-- LCDC RGB or DTV (external) -->
54 <value name="FRAME_LINEAR" value="0"/>
59 <value name="SCALE_FIR" value="0"/>
66 <bitfield name="PIPE0" low="0" high="2" type="mdp_mixer_stage_id"/>
85 <bitfield name="OVERLAY0_DONE" pos="0" type="boolean"/>
102 <reg32 offset="0x00000" name="VERSION">
111 <reg32 offset="0x00004" name="OVLP0_KICK"/>
112 <reg32 offset="0x00008" name="OVLP1_KICK"/>
113 <reg32 offset="0x000d0" name="OVLP2_KICK"/>
114 <reg32 offset="0x0000c" name="DMA_P_KICK"/>
115 <reg32 offset="0x00010" name="DMA_S_KICK"/>
116 <reg32 offset="0x00014" name="DMA_E_KICK"/>
117 <reg32 offset="0x00018" name="DISP_STATUS"/>
119 <reg32 offset="0x00038" name="DISP_INTF_SEL">
120 <bitfield name="PRIM" low="0" high="1" type="mdp4_intf"/>
126 <reg32 offset="0x0003c" name="RESET_STATUS"/> <!-- only mdp4 >v2.1 -->
127 <reg32 offset="0x0004c" name="READ_CNFG"/> <!-- something about # of pending requests.. -->
128 <reg32 offset="0x00050" name="INTR_ENABLE" type="MDP4_IRQ"/>
129 <reg32 offset="0x00054" name="INTR_STATUS" type="MDP4_IRQ"/>
130 <reg32 offset="0x00058" name="INTR_CLEAR" type="MDP4_IRQ"/>
131 <reg32 offset="0x00060" name="EBI2_LCD0"/>
132 <reg32 offset="0x00064" name="EBI2_LCD1"/>
133 <reg32 offset="0x00070" name="PORTMAP_MODE"/>
136 <reg32 offset="0x000c0" name="CS_CONTROLLER0"/>
137 <reg32 offset="0x000c4" name="CS_CONTROLLER1"/>
139 <reg32 offset="0x100f0" name="LAYERMIXER2_IN_CFG" type="mdp4_layermixer_in_cfg"/>
140 <reg32 offset="0x100fc" name="LAYERMIXER_IN_CFG_UPDATE_METHOD"/>
141 <reg32 offset="0x10100" name="LAYERMIXER_IN_CFG" type="mdp4_layermixer_in_cfg"/>
143 <reg32 offset="0x30050" name="VG2_SRC_FORMAT"/>
144 <reg32 offset="0x31008" name="VG2_CONST_COLOR"/>
146 <reg32 offset="0x18000" name="OVERLAY_FLUSH">
147 <bitfield name="OVLP0" pos="0" type="boolean"/>
155 <array offsets="0x10000,0x18000,0x88000" name="OVLP" length="3" stride="0x8000">
156 <reg32 offset="0x0004" name="CFG"/>
157 <reg32 offset="0x0008" name="SIZE" type="reg_wh"/>
158 <reg32 offset="0x000c" name="BASE"/>
159 <reg32 offset="0x0010" name="STRIDE" type="uint"/>
160 <reg32 offset="0x0014" name="OPMODE"/>
162 <array offsets="0x0104,0x0124,0x0144,0x0160" name="STAGE" length="4" stride="0x1c">
163 <reg32 offset="0x00" name="OP">
164 <bitfield name="FG_ALPHA" low="0" high="1" type="mdp_alpha_type"/>
173 <reg32 offset="0x04" name="FG_ALPHA"/>
174 <reg32 offset="0x08" name="BG_ALPHA"/>
175 <reg32 offset="0x0c" name="TRANSP_LOW0"/>
176 <reg32 offset="0x10" name="TRANSP_LOW1"/>
177 <reg32 offset="0x14" name="TRANSP_HIGH0"/>
178 <reg32 offset="0x18" name="TRANSP_HIGH1"/>
181 <array offsets="0x1004,0x1404,0x1804,0x1b84" name="STAGE_CO3" length="4" stride="4">
182 <reg32 offset="0" name="SEL">
183 <bitfield name="FG_ALPHA" pos="0" type="boolean"/> <!-- otherwise bg alpha -->
187 <reg32 offset="0x0180" name="TRANSP_LOW0"/>
188 <reg32 offset="0x0184" name="TRANSP_LOW1"/>
189 <reg32 offset="0x0188" name="TRANSP_HIGH0"/>
190 <reg32 offset="0x018c" name="TRANSP_HIGH1"/>
192 <reg32 offset="0x0200" name="CSC_CONFIG"/>
194 <array offset="0x2000" name="CSC" length="1" stride="0x700">
195 <array offset="0x400" name="MV" length="9" stride="4">
196 <reg32 offset="0" name="VAL"/>
198 <array offset="0x500" name="PRE_BV" length="3" stride="4">
199 <reg32 offset="0" name="VAL"/>
201 <array offset="0x580" name="POST_BV" length="3" stride="4">
202 <reg32 offset="0" name="VAL"/>
204 <array offset="0x600" name="PRE_LV" length="6" stride="4">
205 <reg32 offset="0" name="VAL"/>
207 <array offset="0x680" name="POST_LV" length="6" stride="4">
208 <reg32 offset="0" name="VAL"/>
214 <value name="DMA_P" value="0"/>
218 <reg32 offset="0x90070" name="DMA_P_OP_MODE"/>
219 <array offset="0x94800" name="LUTN" length="2" stride="0x400">
220 <array offset="0" name="LUT" length="0x100" stride="4">
221 <reg32 offset="0" name="VAL"/>
224 <reg32 offset="0xa0028" name="DMA_S_OP_MODE"/>
226 <reg32 offset="0xb0070" name="DMA_E_QUANT" length="3" stride="4"/>
227 <array offsets="0x90000,0xa0000,0xb0000" name="DMA" length="3" stride="0x10000" index="mdp4_dma">
228 <reg32 offset="0x0000" name="CONFIG">
229 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
238 <reg32 offset="0x0004" name="SRC_SIZE" type="reg_wh"/>
239 <reg32 offset="0x0008" name="SRC_BASE"/>
240 <reg32 offset="0x000c" name="SRC_STRIDE" type="uint"/>
241 <reg32 offset="0x0010" name="DST_SIZE" type="reg_wh"/>
243 <reg32 offset="0x0044" name="CURSOR_SIZE">
245 <bitfield name="WIDTH" low="0" high="6" type="uint"/>
248 <reg32 offset="0x0048" name="CURSOR_BASE"/>
249 <reg32 offset="0x004c" name="CURSOR_POS">
250 <bitfield name="X" low="0" high="15" type="uint"/>
253 <reg32 offset="0x0060" name="CURSOR_BLEND_CONFIG">
254 <bitfield name="CURSOR_EN" pos="0" type="boolean"/>
258 <reg32 offset="0x0064" name="CURSOR_BLEND_PARAM"/>
259 <reg32 offset="0x0068" name="BLEND_TRANS_LOW"/>
260 <reg32 offset="0x006c" name="BLEND_TRANS_HIGH"/>
262 <reg32 offset="0x1004" name="FETCH_CONFIG"/>
263 <array offset="0x3000" name="CSC" length="1" stride="0x700">
264 <array offset="0x400" name="MV" length="9" stride="4">
265 <reg32 offset="0" name="VAL"/>
267 <array offset="0x500" name="PRE_BV" length="3" stride="4">
268 <reg32 offset="0" name="VAL"/>
270 <array offset="0x580" name="POST_BV" length="3" stride="4">
271 <reg32 offset="0" name="VAL"/>
273 <array offset="0x600" name="PRE_LV" length="6" stride="4">
274 <reg32 offset="0" name="VAL"/>
276 <array offset="0x680" name="POST_LV" length="6" stride="4">
277 <reg32 offset="0" name="VAL"/>
286 <array offset="0x20000" name="PIPE" length="6" stride="0x10000" index="mdp4_pipe">
287 <reg32 offset="0x0000" name="SRC_SIZE" type="reg_wh"/>
288 <reg32 offset="0x0004" name="SRC_XY" type="reg_xy"/>
289 <reg32 offset="0x0008" name="DST_SIZE" type="reg_wh"/>
290 <reg32 offset="0x000c" name="DST_XY" type="reg_xy"/>
291 <reg32 offset="0x0010" name="SRCP0_BASE"/>
292 <reg32 offset="0x0014" name="SRCP1_BASE"/>
293 <reg32 offset="0x0018" name="SRCP2_BASE"/>
294 <reg32 offset="0x001c" name="SRCP3_BASE"/>
295 <reg32 offset="0x0040" name="SRC_STRIDE_A">
296 <bitfield name="P0" low="0" high="15" type="uint"/>
299 <reg32 offset="0x0044" name="SRC_STRIDE_B">
300 <bitfield name="P2" low="0" high="15" type="uint"/>
303 <reg32 offset="0x0048" name="SSTILE_FRAME_SIZE" type="reg_wh"/>
304 <reg32 offset="0x0050" name="SRC_FORMAT">
305 <bitfield name="G_BPC" low="0" high="1" type="mdp_bpc"/>
322 <reg32 offset="0x0054" name="SRC_UNPACK" type="mdp_unpack_pattern"/>
323 <reg32 offset="0x0058" name="OP_MODE">
324 <bitfield name="SCALEX_EN" pos="0" type="boolean"/>
338 <reg32 offset="0x005c" name="PHASEX_STEP"/>
339 <reg32 offset="0x0060" name="PHASEY_STEP"/>
340 <reg32 offset="0x1004" name="FETCH_CONFIG"/>
341 <reg32 offset="0x1008" name="SOLID_COLOR"/>
343 <array offset="0x4000" name="CSC" length="1" stride="0x700">
344 <array offset="0x400" name="MV" length="9" stride="4">
345 <reg32 offset="0" name="VAL"/>
347 <array offset="0x500" name="PRE_BV" length="3" stride="4">
348 <reg32 offset="0" name="VAL"/>
350 <array offset="0x580" name="POST_BV" length="3" stride="4">
351 <reg32 offset="0" name="VAL"/>
353 <array offset="0x600" name="PRE_LV" length="6" stride="4">
354 <reg32 offset="0" name="VAL"/>
356 <array offset="0x680" name="POST_LV" length="6" stride="4">
357 <reg32 offset="0" name="VAL"/>
369 <bitfield name="HSYNC_LOW" pos="0" type="boolean"/>
375 <bitfield name="START" low="0" high="14" type="uint"/>
381 <bitfield name="START" low="0" high="15" type="uint"/>
386 <bitfield name="PULSEW" low="0" high="15" type="uint"/>
391 <bitfield name="COLOR" low="0" high="23"/>
395 <!-- offset is 0xe0000 on !mdp4.. -->
396 <array offset="0xc0000" name="LCDC" length="1" stride="0x1000">
397 <reg32 offset="0x0000" name="ENABLE"/>
398 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
399 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
400 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
401 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
402 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
403 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
404 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
405 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
406 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
407 <reg32 offset="0x0028" name="BORDER_CLR"/>
408 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
409 <reg32 offset="0x0030" name="HSYNC_SKEW"/>
410 <reg32 offset="0x0034" name="TEST_CNTL"/>
411 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
414 <reg32 offset="0xc2000" name="LCDC_LVDS_INTF_CTL">
433 <array offset="0xc2014" name="LCDC_LVDS_MUX_CTL" length="4" stride="0x8">
434 <reg32 offset="0x0" name="3_TO_0">
435 <bitfield name="BIT0" low="0" high="7"/>
440 <reg32 offset="0x4" name="6_TO_4">
441 <bitfield name="BIT4" low="0" high="7"/>
447 <reg32 offset="0xc2034" name="LCDC_LVDS_PHY_RESET"/>
449 <reg32 offset="0xc3000" name="LVDS_PHY_PLL_CTRL_0"/>
450 <reg32 offset="0xc3004" name="LVDS_PHY_PLL_CTRL_1"/>
451 <reg32 offset="0xc3008" name="LVDS_PHY_PLL_CTRL_2"/>
452 <reg32 offset="0xc300c" name="LVDS_PHY_PLL_CTRL_3"/>
453 <reg32 offset="0xc3014" name="LVDS_PHY_PLL_CTRL_5"/>
454 <reg32 offset="0xc3018" name="LVDS_PHY_PLL_CTRL_6"/>
455 <reg32 offset="0xc301c" name="LVDS_PHY_PLL_CTRL_7"/>
456 <reg32 offset="0xc3020" name="LVDS_PHY_PLL_CTRL_8"/>
457 <reg32 offset="0xc3024" name="LVDS_PHY_PLL_CTRL_9"/>
458 <reg32 offset="0xc3080" name="LVDS_PHY_PLL_LOCKED"/>
459 <reg32 offset="0xc3108" name="LVDS_PHY_CFG2"/>
461 <reg32 offset="0xc3100" name="LVDS_PHY_CFG0">
467 <array offset="0xd0000" name="DTV" length="1" stride="0x1000">
468 <reg32 offset="0x0000" name="ENABLE"/>
469 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
470 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
471 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
472 <reg32 offset="0x0018" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
473 <reg32 offset="0x001c" name="DISPLAY_VSTART" type="uint"/>
474 <reg32 offset="0x0020" name="DISPLAY_VEND" type="uint"/>
475 <reg32 offset="0x002c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
476 <reg32 offset="0x0030" name="ACTIVE_VSTART" type="uint"/>
477 <reg32 offset="0x0038" name="ACTIVE_VEND" type="uint"/>
478 <reg32 offset="0x0040" name="BORDER_CLR"/>
479 <reg32 offset="0x0044" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
480 <reg32 offset="0x0048" name="HSYNC_SKEW"/>
481 <reg32 offset="0x004c" name="TEST_CNTL"/>
482 <reg32 offset="0x0050" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>
485 <array offset="0xe0000" name="DSI" length="1" stride="0x1000">
486 <reg32 offset="0x0000" name="ENABLE"/>
487 <reg32 offset="0x0004" name="HSYNC_CTRL" type="mdp4_hsync_ctrl"/>
488 <reg32 offset="0x0008" name="VSYNC_PERIOD" type="uint"/>
489 <reg32 offset="0x000c" name="VSYNC_LEN" type="uint"/>
490 <reg32 offset="0x0010" name="DISPLAY_HCTRL" type="mdp4_display_hctl"/>
491 <reg32 offset="0x0014" name="DISPLAY_VSTART" type="uint"/>
492 <reg32 offset="0x0018" name="DISPLAY_VEND" type="uint"/>
493 <reg32 offset="0x001c" name="ACTIVE_HCTL" type="mdp4_active_hctl"/>
494 <reg32 offset="0x0020" name="ACTIVE_VSTART" type="uint"/>
495 <reg32 offset="0x0024" name="ACTIVE_VEND" type="uint"/>
496 <reg32 offset="0x0028" name="BORDER_CLR"/>
497 <reg32 offset="0x002c" name="UNDERFLOW_CLR" type="mdp4_underflow_clr"/>
498 <reg32 offset="0x0030" name="HSYNC_SKEW"/>
499 <reg32 offset="0x0034" name="TEST_CNTL"/>
500 <reg32 offset="0x0038" name="CTRL_POLARITY" type="mdp4_ctrl_polarity"/>