Lines Matching +full:0 +full:x000a8
9 <value name="NON_BURST_SYNCH_PULSE" value="0"/>
14 <value name="VID_DST_FORMAT_RGB565" value="0"/>
20 <value name="SWAP_RGB" value="0"/>
28 <value name="TRIGGER_NONE" value="0"/>
36 <value name="CMD_DST_FORMAT_RGB111" value="0"/>
44 <value name="LANE_SWAP_0123" value="0"/>
54 <value name="VIDEO_CONFIG_18BPP" value="0"/>
58 <value name="VID_PRBS" value="0"/>
64 <value name="CMD_MDP_PRBS" value="0"/>
70 <value name="CMD_DMA_PRBS" value="0"/>
76 <bitfield name="CMD_DMA_DONE" pos="0" type="boolean"/>
88 <reg32 offset="0x00000" name="6G_HW_VERSION">
91 <bitfield name="STEP" low="0" high="15" type="uint"/>
94 <reg32 offset="0x00000" name="CTRL">
95 <bitfield name="ENABLE" pos="0" type="boolean"/>
107 <reg32 offset="0x00004" name="STATUS0">
108 <bitfield name="CMD_MODE_ENGINE_BUSY" pos="0" type="boolean"/>
116 <reg32 offset="0x00008" name="FIFO_STATUS">
117 <bitfield name="VIDEO_MDP_FIFO_OVERFLOW" pos="0" type="boolean"/>
143 <reg32 offset="0x0000c" name="VID_CFG0">
144 <bitfield name="VIRT_CHANNEL" low="0" high="1" type="uint"/> <!-- always zero? -->
155 <reg32 offset="0x0001c" name="VID_CFG1">
156 <bitfield name="R_SEL" pos="0" type="boolean"/>
161 <reg32 offset="0x00020" name="ACTIVE_H">
162 <bitfield name="START" low="0" high="11" type="uint"/>
165 <reg32 offset="0x00024" name="ACTIVE_V">
166 <bitfield name="START" low="0" high="11" type="uint"/>
169 <reg32 offset="0x00028" name="TOTAL">
170 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
173 <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
174 <bitfield name="START" low="0" high="11" type="uint"/>
177 <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
178 <bitfield name="START" low="0" high="11" type="uint"/>
181 <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
182 <bitfield name="START" low="0" high="11" type="uint"/>
186 <reg32 offset="0x00038" name="CMD_DMA_CTRL">
191 <reg32 offset="0x0003c" name="CMD_CFG0">
192 <bitfield name="DST_FORMAT" low="0" high="3" type="dsi_cmd_dst_format"/>
199 <reg32 offset="0x00040" name="CMD_CFG1">
200 <bitfield name="WR_MEM_START" low="0" high="7" type="uint"/>
204 <reg32 offset="0x00044" name="DMA_BASE"/>
205 <reg32 offset="0x00048" name="DMA_LEN"/>
206 <reg32 offset="0x00054" name="CMD_MDP_STREAM0_CTRL">
207 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
211 <reg32 offset="0x00058" name="CMD_MDP_STREAM0_TOTAL">
212 <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
215 <reg32 offset="0x0005c" name="CMD_MDP_STREAM1_CTRL">
216 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
220 <reg32 offset="0x00060" name="CMD_MDP_STREAM1_TOTAL">
221 <bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
224 <reg32 offset="0x00064" name="ACK_ERR_STATUS"/>
225 <array offset="0x00068" name="RDBK" length="4" stride="4">
226 <reg32 offset="0x0" name="DATA"/>
228 <reg32 offset="0x00080" name="TRIG_CTRL">
229 <bitfield name="DMA_TRIGGER" low="0" high="2" type="dsi_cmd_trigger"/>
235 <reg32 offset="0x0008c" name="TRIG_DMA"/>
236 <reg32 offset="0x000b0" name="DLN0_PHY_ERR">
237 <bitfield name="DLN0_ERR_ESC" pos="0" type="boolean"/>
243 <reg32 offset="0x000b4" name="LP_TIMER_CTRL">
244 <bitfield name="LP_RX_TO" low="0" high="15" type="uint"/>
247 <reg32 offset="0x000b8" name="HS_TIMER_CTRL">
248 <bitfield name="HS_TX_TO" low="0" high="15" type="uint"/>
252 <reg32 offset="0x000bc" name="TIMEOUT_STATUS"/>
253 <reg32 offset="0x000c0" name="CLKOUT_TIMING_CTRL">
254 <bitfield name="T_CLK_PRE" low="0" high="5" type="uint"/>
257 <reg32 offset="0x000c8" name="EOT_PACKET_CTRL">
258 <bitfield name="TX_EOT_APPEND" pos="0" type="boolean"/>
261 <reg32 offset="0x000a4" name="LANE_STATUS">
262 <bitfield name="DLN0_STOPSTATE" pos="0" type="boolean"/>
274 <reg32 offset="0x000a8" name="LANE_CTRL">
278 <reg32 offset="0x000ac" name="LANE_SWAP_CTRL">
279 <bitfield name="DLN_SWAP_SEL" low="0" high="2" type="dsi_lane_swap"/>
281 <reg32 offset="0x00108" name="ERR_INT_MASK0"/>
282 <reg32 offset="0x0010c" name="INTR_CTRL" type="DSI_IRQ"/>
283 <reg32 offset="0x00114" name="RESET"/>
284 <reg32 offset="0x00118" name="CLK_CTRL">
285 <bitfield name="AHBS_HCLK_ON" pos="0" type="boolean"/>
293 <reg32 offset="0x0011c" name="CLK_STATUS">
294 <bitfield name="DSI_AON_AHBM_HCLK_ACTIVE" pos="0" type="boolean"/>
311 <reg32 offset="0x00128" name="PHY_RESET">
312 <bitfield name="RESET" pos="0" type="boolean"/>
314 <reg32 offset="0x00160" name="TEST_PATTERN_GEN_VIDEO_INIT_VAL"/>
315 <reg32 offset="0x00198" name="TPG_MAIN_CONTROL">
318 <reg32 offset="0x001a0" name="TPG_VIDEO_CONFIG">
319 <bitfield name="BPP" low="0" high="1" type="video_config_bpp"/>
322 <reg32 offset="0x00158" name="TEST_PATTERN_GEN_CTRL">
328 <bitfield name="EN" pos="0" type="boolean"/>
330 <reg32 offset="0x00168" name="TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0"/>
331 <reg32 offset="0x00180" name="TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER">
332 <bitfield name="SW_TRIGGER" pos="0" type="boolean"/>
334 <reg32 offset="0x0019c" name="TPG_MAIN_CONTROL2">
339 <reg32 offset="0x0017c" name="T_CLK_PRE_EXTEND">
340 <bitfield name="INC_BY_2_BYTECLK" pos="0" type="boolean"/>
342 <reg32 offset="0x001b4" name="CMD_MODE_MDP_CTRL2">
343 <bitfield name="DST_FORMAT2" low="0" high="3" type="dsi_cmd_dst_format"/>
353 <reg32 offset="0x001b8" name="CMD_MODE_MDP_STREAM2_CTRL">
354 <bitfield name="DATA_TYPE" low="0" high="5" type="uint"/>
358 <reg32 offset="0x001d0" name="RDBK_DATA_CTRL">
360 <bitfield name="CLR" pos="0" type="boolean"/>
362 <reg32 offset="0x001f0" name="VERSION">
365 <reg32 offset="0x002d4" name="CPHY_MODE_CTRL"/>
366 <reg32 offset="0x0029c" name="VIDEO_COMPRESSION_MODE_CTRL">
371 <bitfield name="EN" pos="0" type="boolean"/>
373 <reg32 offset="0x002a4" name="COMMAND_COMPRESSION_MODE_CTRL">
381 <bitfield name="STREAM0_EN" pos="0" type="boolean"/>
383 <reg32 offset="0x002a8" name="COMMAND_COMPRESSION_MODE_CTRL2">
385 <bitfield name="STREAM0_SLICE_WIDTH" low="0" high="15" type="uint"/>