Lines Matching +full:low +full:-
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
9 <!--
12 - "cmd" - the register is used outside of renderpass and blits,
14 - "rp_blit" - the register is used inside renderpass or blits
21 -->
23 <!-- these might be same as a5xx -->
39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
121 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
122 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
123 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
125 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
129 <!-- Note: tiling/UBWC for these may be different from equivalent formats
131 -->
180 <!-- for sampling stencil (integer, 2nd channel), not available on a630 -->
183 <!-- Not a hw enum, used internally in driver -->
188 <!-- probably same as a5xx -->
203 <bitfield name="BASE_ADDR" low="0" high="17"/>
204 <bitfield name="MASK_LEN" low="18" high="30"/>
1121 <!--
1137 -->
1150 <doc>Allow early z-test and early-lrz (if applicable)</doc>
1152 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
1155 A special mode that allows early-lrz test but disables
1156 early-z test. Which might sound a bit funny, since
1157 lrz-test happens before z-test. But as long as a couple
1158 conditions are maintained this allows using lrz-test in
1161 1) Disable lrz-write in cases where it is uncertain during
1163 shader has-kill, writes-z, or alpha/stencil test is
1164 enabled. (For correctness, lrz-write must be disabled
1166 z-prepass works.
1168 2) Disable lrz-write and test if a depth-test direction
1173 lrz-test. But geometry which may be (or contributes to
1174 blend) will pass the lrz-test.
1176 This allows us to keep early-lrz-test in cases where the frag
1177 shader does not write-z (ie. we know the z-value before FS)
1178 and does not have side-effects (image/ssbo writes, etc), but
1180 enough case that it is useful to keep early-lrz test against
2226 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/>
2227 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/>
2238 <!-- Same as above but different name??: -->
2239 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/>
2240 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/>
2244 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/>
2251 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/>
2252 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/>
2257 <!--
2260 -->
2269 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/>
2270 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/>
2271 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/>
2272 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/>
2273 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/>
2274 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/>
2275 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/>
2276 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/>
2277 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/>
2278 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/>
2297 <!-- Crashdumper writes -->
2299 <!-- Crashdumper reads -->
2302 <!-- 4 is unknown -->
2304 <!-- RPTR shadow writes -->
2306 <!-- Memory accesses from PM4 packets in the ringbuffer -->
2308 <!-- Ringbuffer reads -->
2310 <!-- Instruction cache fetches -->
2313 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: -->
2315 <!-- all the threshold values seem to be in units of quad-dwords: -->
2323 <bitfield name="MRB_START" low="0" high="7" shr="2"/>
2324 <bitfield name="VSD_START" low="8" high="15" shr="2"/>
2325 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
2326 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
2330 low bits identify where CP_SET_DRAW_STATE stateobj
2340 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
2341 <!-- total ROQ size: -->
2342 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
2363 <bitfield name="LEVEL" low="6" high="7"/>
2371 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
2373 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
2391 <!-- SDS == CP_SET_DRAW_STATE: -->
2394 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
2397 <!--
2400 -->
2404 <bitfield name="RPTR" low="0" high="9"/>
2405 <bitfield name="WPTR" low="16" high="25"/>
2422 <bitfield name="REM" low="16" high="31"/>
2426 <bitfield name="REM" low="16" high="31"/>
2430 <bitfield name="REM" low="16" high="31"/>
2434 <bitfield name="REM" low="16" high="31"/>
2438 <bitfield name="REM" low="16" high="31"/>
2442 <bitfield name="REM" low="16" high="31"/>
2446 <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/>
2447 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/>
2448 <bitfield name="CONTEXT" low="4" high="5"/>
2453 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
2455 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
2457 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
2458 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
2459 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
2460 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
2461 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
2462 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
2463 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
2464 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
2465 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
2466 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
2467 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
2468 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
2469 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
2471 <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
2472 <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
2473 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
2474 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
2476 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
2477 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
2478 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
2479 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
2480 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
2481 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
2482 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
2484 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
2486 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
2487 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
2488 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
2492 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
2493 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
2494 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
2496 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
2497 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
2498 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
2499 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
2500 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
2501 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
2502 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
2503 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
2504 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
2505 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
2506 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
2507 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
2545 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
2546 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
2547 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
2548 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
2549 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
2550 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
2552 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
2553 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
2572 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
2573 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
2574 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
2575 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
2576 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
2577 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
2578 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
2579 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
2580 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
2581 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
2582 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
2583 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
2584 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
2585 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
2586 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
2587 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
2588 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
2589 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
2590 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
2591 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
2592 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
2593 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
2594 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
2595 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
2596 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
2597 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
2598 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
2599 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
2614 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
2616 <!---
2620 -->
2622 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
2624 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
2626 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
2628 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
2630 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
2632 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
2634 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
2636 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
2638 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
2640 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
2650 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
2659 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
2660 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
2664 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
2670 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
2778 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
2779 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
2783 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
2795 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
2802 <bitfield high="7" low="0" name="PING_INDEX"/>
2803 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
2806 <bitfield high="5" low="0" name="TRACEEN"/>
2807 <bitfield high="14" low="12" name="GRANU"/>
2808 <bitfield high="31" low="28" name="SEGT"/>
2811 <bitfield high="27" low="24" name="ENABLE"/>
2822 <bitfield high="3" low="0" name="BYTEL0"/>
2823 <bitfield high="7" low="4" name="BYTEL1"/>
2824 <bitfield high="11" low="8" name="BYTEL2"/>
2825 <bitfield high="15" low="12" name="BYTEL3"/>
2826 <bitfield high="19" low="16" name="BYTEL4"/>
2827 <bitfield high="23" low="20" name="BYTEL5"/>
2828 <bitfield high="27" low="24" name="BYTEL6"/>
2829 <bitfield high="31" low="28" name="BYTEL7"/>
2832 <bitfield high="3" low="0" name="BYTEL8"/>
2833 <bitfield high="7" low="4" name="BYTEL9"/>
2834 <bitfield high="11" low="8" name="BYTEL10"/>
2835 <bitfield high="15" low="12" name="BYTEL11"/>
2836 <bitfield high="19" low="16" name="BYTEL12"/>
2837 <bitfield high="23" low="20" name="BYTEL13"/>
2838 <bitfield high="27" low="24" name="BYTEL14"/>
2839 <bitfield high="31" low="28" name="BYTEL15"/>
2862 <bitfield high="7" low="0" name="PERFSEL"/>
2878 <bitfield low="0" high="3" name="DATA_SEL"/>
2882 <bitfield low="0" high="8" name="DATA_SEL"/>
2936 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
2937 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
2941 <bitfield name="NX" low="1" high="10" type="uint"/>
2942 <bitfield name="NY" low="11" high="20" type="uint"/>
2954 <bitfield name="X" low="0" high="9" type="uint"/>
2955 <bitfield name="Y" low="10" high="19" type="uint"/>
2956 <bitfield name="W" low="20" high="25" type="uint"/>
2957 <bitfield name="H" low="26" high="31" type="uint"/>
2960 <!--
2963 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
2968 LIMIT is set to PITCH - 64, to make room for a bit of overflow
2969 -->
3004 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
3006 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
3007 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
3008 <!-- always 0x03200000 ? -->
3011 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
3013 <bitfield name="X" low="0" high="13" type="uint"/>
3014 <bitfield name="Y" low="16" high="29" type="uint"/>
3022 <!-- controls near z clip behavior (set for vulkan) -->
3024 <!-- guess based on a3xx and meaning of bits 8 and 9
3025 if the guess is right then this is related to point sprite clipping -->
3032 <bitfield name="CLIP_MASK" low="0" high="7"/>
3033 <bitfield name="CULL_MASK" low="8" high="15"/>
3038 <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>
3041 <!-- see also RB_RENDER_CONTROL0 -->
3048 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
3049 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/>
3050 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/>
3053 <bitfield name="HORZ" low="0" high="8" type="uint"/>
3054 <bitfield name="VERT" low="10" high="18" type="uint"/>
3057 <!-- Something connected to depth-stencil attachment size -->
3058 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
3060 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
3062 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
3063 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
3064 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
3065 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
3067 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
3069 <!-- 0x8006-0x800f invalid -->
3087 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
3091 <bitfield name="UNK15" low="15" high="16"/>
3092 <!--
3101 -->
3105 <bitfield name="UNK20" low="20" high="22"/>
3108 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
3109 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
3111 …<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="r…
3112 <!-- 0x8093 invalid -->
3114 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3119 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
3121 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3127 <bitfield name="SHIFTAMOUNT" low="1" high="2"/>
3129 <bitfield name="UNK4" low="4" high="5"/>
3143 <!-- 0x809e/0x809f invalid -->
3157 flushed before the data or vice-versa, leading to
3162 non-coherent blending.
3177 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE -->
3183 <!-- I'm guessing this is the same as a3xx -->
3192 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
3193 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/>
3195 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/>
3197 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set -->
3199 <bitfield name="ROTATION" low="10" high="11" type="uint"/>
3217 <!-- We don't have a flag type and this flags combination is often used -->
3223 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3224 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3225 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3228 …<bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/>
3234 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3239 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3244 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3254 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
3255 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
3256 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
3257 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
3258 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
3259 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
3260 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
3261 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
3268 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
3270 <!-- 0x80a7-0x80ae invalid -->
3274 <bitfield name="X" low="0" high="15" type="uint"/>
3275 <bitfield name="Y" low="16" high="31" type="uint"/>
3289 <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
3290 <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
3291 <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
3292 <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
3293 <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
3294 <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
3295 <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
3311 - 0.0 if GREATER
3312 - 1.0 if LESS
3315 <!-- set when depth-test + depth-write enabled -->
3318 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/>
3320 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into
3326 If DIR_WRITE is not enabled - there is no write to direction buffer.
3329 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/>
3337 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
3339 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/>
3343 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3347 <!-- TODO: fix the shr fields -->
3348 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
3349 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
3352 <!--
3375 // fast-clear buffer is 1bit/block:
3381 -->
3383 <!-- 0x8108 invalid -->
3387 <!--
3393 the value stored in the LRZ buffer, if not - LRZ is disabled.
3394 -->
3396 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
3397 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/>
3398 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/>
3401 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">
3406 <!-- 0x810c-0x810f invalid -->
3408 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>
3410 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR -->
3411 <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
3413 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3414 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3418 <!-- Always written together and always equal 09510840 00000a62 -->
3419 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
3420 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
3422 <!-- 0x8112-0x83ff invalid -->
3434 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
3436 <bitfield name="UNK4" low="4" high="6"/>
3438 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
3440 <bitfield name="UNK17" low="17" high="18"/>
3441 <!-- required when blitting D24S8/D24X8 -->
3443 <!-- some sort of channel mask, disabled channels are set to zero ? -->
3444 <bitfield name="MASK" low="20" high="23"/>
3445 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
3447 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/>
3451 <!-- note: the low 8 bits for src coords are valid, probably fixed point
3454 -->
3455 <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>
3456 <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>
3457 <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>
3458 <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>
3461 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
3462 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
3463 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
3466 <!-- 0x840c-0x85ff invalid -->
3468 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
3474 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
3479 <!-- note 0x8620-0x87ff are not all invalid
3481 -->
3483 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
3485 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3486 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3487 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3489 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/>
3490 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3493 <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
3494 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3495 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3496 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/>
3498 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/>
3502 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/>
3504 <!-- set during binning pass: -->
3506 <bitfield name="UNK8" low="8" high="10"/>
3508 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
3511 <!-- bit seems to be set whenever depth buffer enabled: -->
3513 <!-- bitmask of MRTs using UBWC flag buffer: -->
3514 <bitfield name="FLAG_MRTS" low="16" high="23"/>
3516 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3518 <!-- set during binning pass: -->
3521 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/>
3525 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3530 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3535 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3542 <!-- 0x8807-0x8808 invalid -->
3543 <!--
3546 -->
3548 <!-- see also GRAS_CNTL -->
3555 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
3559 <!-- enable bits for various FS sysvalue regs: -->
3564 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>
3577 <bitfield name="MRT" low="0" high="3" type="uint"/>
3580 <bitfield name="RT0" low="0" high="3"/>
3581 <bitfield name="RT1" low="4" high="7"/>
3582 <bitfield name="RT2" low="8" high="11"/>
3583 <bitfield name="RT3" low="12" high="15"/>
3584 <bitfield name="RT4" low="16" high="19"/>
3585 <bitfield name="RT5" low="20" high="23"/>
3586 <bitfield name="RT6" low="24" high="27"/>
3587 <bitfield name="RT7" low="28" high="31"/>
3590 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
3591 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
3592 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
3593 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
3594 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
3595 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
3596 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/>
3597 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
3600 <!-- Same as SP_SRGB_CNTL -->
3614 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
3615 <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
3616 <!-- 0x8813-0x8817 invalid -->
3617 <!-- always 0x0 ? -->
3618 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
3619 <!-- 0x8819-0x881e all 32 bits -->
3626 <!-- 0x881f invalid -->
3632 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
3633 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
3636 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
3637 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
3638 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
3639 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
3640 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
3641 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
3644 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3645 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3647 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
3649 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
3650 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3651 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3654 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
3655 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3657 <!--
3660 -->
3663 <!--
3668 -->
3669 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
3672 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
3680 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
3682 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
3685 <!-- per-mrt enable bit -->
3686 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
3691 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
3693 <!-- 0x8866-0x886f invalid -->
3695 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3701 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
3713 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
3715 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3716 <bitfield name="UNK3" low="3" high="4"/>
3718 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO -->
3719 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3720 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3721 <bitfield name="UNK3" low="3" high="4"/>
3722 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/>
3726 …<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="r…
3727 …<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" us…
3729 …<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit…
3733 <!-- 0x887a-0x887f invalid -->
3737 <!--
3742 -->
3744 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
3745 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
3746 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
3747 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
3748 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
3749 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
3750 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
3751 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
3760 <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
3763 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/>
3765 …<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage=…
3766 …<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" …
3768 …<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_bl…
3770 <bitfield name="REF" low="0" high="7"/>
3771 <bitfield name="BFREF" low="8" high="15"/>
3774 <bitfield name="MASK" low="0" high="7"/>
3775 <bitfield name="BFMASK" low="8" high="15"/>
3778 <bitfield name="WRMASK" low="0" high="7"/>
3779 <bitfield name="BFWRMASK" low="8" high="15"/>
3781 <!-- 0x888a-0x888f invalid -->
3787 <!-- 0x8892-0x8897 invalid -->
3791 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
3792 <!-- 0x8899-0x88bf invalid -->
3793 <!-- clamps depth value for depth test/write -->
3796 <!-- 0x88c2-0x88cf invalid-->
3798 <bitfield name="UNK0" low="0" high="12"/>
3799 <bitfield name="UNK16" low="16" high="26"/>
3803 <!-- weird to duplicate other regs from same block?? -->
3805 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3806 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
3810 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
3812 <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
3813 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
3815 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3817 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
3818 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
3819 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
3821 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/>
3824 …<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_bl…
3825 <!-- array-pitch is size of layer -->
3826 …<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage=…
3829 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3830 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
3838 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
3840 …bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color resto…
3841 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
3842 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
3843 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
3846 1 - depth
3847 2 - stencil
3848 3 - depth+stencil
3852 <bitfield name="CLEAR_MASK" low="4" high="7"/>
3853 <!-- set when this is the last resolve on a650+ -->
3854 <bitfield name="LAST" low="8" high="9"/>
3855 <!--
3860 -->
3861 <bitfield name="BUFFER_ID" low="12" high="15"/>
3863 <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
3864 <!-- Value conditioned based on predicate, changed before blits -->
3874 <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
3877 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
3878 <!-- GMEM offset of CCU depth cache -->
3879 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
3880 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
3881 <!-- GMEM offset of CCU color cache
3886 -->
3887 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
3889 <!-- 0x88e6-0x88ef invalid -->
3890 <!-- always 0x0 ? -->
3891 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
3892 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
3895 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3896 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
3898 <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
3899 <!-- Connected to VK_EXT_fragment_density_map? -->
3900 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
3901 <!-- 0x88f6-0x88ff invalid -->
3904 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
3905 <!-- TODO: actually part of array pitch -->
3906 <bitfield name="UNK8" low="8" high="10"/>
3907 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
3912 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3913 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
3916 <!-- 0x891b-0x8926 invalid -->
3922 <!-- 0x8929-0x89ff invalid -->
3924 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
3926 <!--
3928 blob writing non-zero:
3929 -->
3936 <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>
3939 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3940 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3941 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
3944 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
3952 <bitfield name="UNK23" low="23" high="26"/>
3954 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/>
3958 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3959 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
3960 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
3963 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
3964 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/>
3967 <!-- 0x8c02-0x8c16 invalid -->
3970 …<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit…
3971 <!-- this is a guess but seems likely (for NV12/IYUV): -->
3973 …<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="r…
3977 …<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp…
3978 <!-- this is a guess but seems likely (for NV12 with UBWC): -->
3980 …<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usa…
3982 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
3983 <!-- unlike a5xx, these are per channel values rather than packed -->
3989 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
3991 <!-- 0x8c35-0x8dff invalid -->
3993 <!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
3995 <!-- 0x8e00-0x8e03 invalid -->
3996 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
3998 <!-- 0x02080000 in GMEM, zero otherwise? -->
3999 <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
4003 <!-- concurrent resolves are apparently a 2-bit enum on a650+ -->
4007 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/>
4008 <!-- GMEM offset of CCU depth cache -->
4009 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/>
4010 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/>
4011 <!-- GMEM offset of CCU color cache
4016 -->
4017 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/>
4018 <!--TODO: valid mask 0xfffffc1f -->
4020 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
4023 <!-- rest of the bits were moved to RB_CCU_CNTL2 -->
4027 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
4028 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
4032 <bitfield name="UNK12" low="12" high="13"/>
4034 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
4035 <!-- 0x8e09-0x8e0f invalid -->
4038 <!-- 0x8e1d-0x8e1f invalid -->
4039 <!-- 0x8e20-0x8e25 more perfcntr sel? -->
4040 <!-- 0x8e26-0x8e27 invalid -->
4042 <!-- 0x8e29-0x8e2b invalid -->
4044 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
4047 <!-- 0x8e3e-0x8e4f invalid -->
4048 <!-- GMEM save/restore for preemption: -->
4050 <!-- address for GMEM save/restore? -->
4052 <!-- 0x8e53-0x8e7f invalid -->
4053 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
4054 <!-- 0x8e80-0x8e83 are valid -->
4055 <!-- 0x8e84-0x90ff invalid -->
4057 <!-- 0x9000-0x90ff invalid -->
4060 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
4064 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
4065 <!-- there can be up to 8 total clip/cull distance outputs,
4068 -->
4069 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/>
4070 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/>
4081 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
4082 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/>
4083 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/>
4095 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused -->
4100 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4120 <!-- TODO: first 16 bits are valid so something is wrong or missing here -->
4121 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
4122 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
4124 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
4132 Multi-position output lets the last geometry
4139 <bitfield name="VIEWS" low="2" high="6" type="uint"/>
4142 …<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" u…
4143 …<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" u…
4144 …<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usa…
4145 …<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage…
4161 <!-- 0x9109-0x91ff invalid -->
4171 <!-- always 0x0 -->
4172 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
4173 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
4176 <!-- one bit per varying component: -->
4181 <!--
4201 This field is auto-incremented when VPC_SO_PROG is
4203 -->
4204 <bitfield name="ADDR" low="0" high="7" type="hex"/>
4205 <!-- clear all A_EN and B_EN bits for all DWORD's -->
4208 <!-- special register, write multiple times to load SO program (not readable) -->
4210 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
4211 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
4213 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
4214 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
4222 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
4223 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
4224 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
4231 <!-- 0x9237-0x92ff invalid -->
4232 <!-- always 0x0 ? -->
4233 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>
4238 plus # of transform-feedback (streamout) varyings if using the
4241 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4242 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
4243 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
4244 <bitfield name="EXTRAPOS" low="24" high="27" type="uint">
4247 number of views minus one when multi-position
4257 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
4258 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS -->
4259 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/>
4261 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint">
4266 strictly required for multi-position output,
4268 views at once, but it can be used when multi-pos
4276 <!--
4278 -->
4279 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
4280 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/>
4281 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/>
4282 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/>
4283 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
4288 <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
4289 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4291 <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4292 <bitfield name="SIZE_GMEM" low="0" high="31"/>
4294 <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
4295 <bitfield name="BASE_GMEM" low="0" high="31"/>
4297 <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4298 <bitfield name="SIZE_GMEM" low="0" high="31"/>
4301 <!-- 0x9307-0x95ff invalid -->
4303 <!-- TODO: 0x9600-0x97ff range -->
4304 …set="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask -…
4306 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
4307 <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
4309 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
4310 <!-- 0x960a-0x9623 invalid -->
4311 <!-- TODO: regs from 0x9624-0x963a -->
4312 <!-- 0x963b-0x97ff invalid -->
4314 <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>
4316 <!-- always 0x0 ? -->
4318 <bitfield name="SIZE" low="0" high="10" type="uint"/>
4323 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
4324 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/>
4327 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>
4328 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>
4330 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
4336 <!-- New in a6xx gen3+ -->
4338 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
4344 <!-- 0x980b-0x983f invalid -->
4346 <!-- 0x9840 - 0x9842 are not readable -->
4348 <bitfield name="STATE_ID" low="0" high="7"/>
4352 <bitfield name="STATE_ID" low="0" high="7"/>
4356 <!-- I think only the low bit is actually used? -->
4357 <bitfield name="STATE_ID" low="16" high="23"/>
4358 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4361 <!--
4365 -->
4368 <!-- 0x9843-0x997f invalid -->
4371 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4373 <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
4374 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4378 <!-- which stream to send to GRAS -->
4379 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4380 <!-- discard primitives before rasterization -->
4383 <!-- VPC_RASTER_CNTL -->
4384 <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
4385 <!-- which stream to send to GRAS -->
4386 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4387 <!-- discard primitives before rasterization -->
4390 <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
4391 <!-- which stream to send to GRAS -->
4392 <bitfield name="STREAM" low="0" high="1" type="uint"/>
4393 <!-- discard primitives before rasterization -->
4397 <!-- Both are a750+.
4399 -->
4400 <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
4401 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
4403 -->
4404 <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
4406 <!-- 0x9982-0x9aff invalid -->
4413 plus # of transform-feedback (streamout) varyings if using the
4416 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4420 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit -->
4422 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/>
4423 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/>
4428 <!-- since HS can't output anything, only PRIMITIVE_ID is valid -->
4436 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC
4438 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
4442 <!-- mask of enabled views, doesn't exist on A630 -->
4443 <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>
4444 <!-- 0x9b09-0x9bff invalid -->
4446 <!-- special register (but note first 8 bits can be written/read) -->
4447 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4448 <bitfield name="STATE_ID" low="8" high="15"/>
4450 <!-- 0x9c01-0x9dff invalid -->
4451 <!-- TODO: 0x9e00-0xa000 range incomplete -->
4458 …<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage…
4469 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
4471 <bitfield name="UNK0" low="0" high="15"/>
4472 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
4473 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
4483 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
4486 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
4488 <!-- always 0x0 -->
4492 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
4493 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/>
4496 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
4497 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
4498 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
4499 <!-- only used for VS in non-multi-position-output case -->
4500 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/>
4503 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
4507 patch within the HS->DS buffers. When a draw is
4513 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
4516 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
4517 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/>
4518 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
4519 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
4522 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
4525 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
4526 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/>
4529 <!--
4531 -->
4536 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
4541 <!-- add VFD_INDEX_OFFSET to REGID4VTX -->
4543 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST -->
4552 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
4556 <!-- IDX and byte OFFSET into VFD_FETCH -->
4557 <bitfield name="IDX" low="0" high="4" type="uint"/>
4558 <bitfield name="OFFSET" low="5" high="16"/>
4560 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/>
4561 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
4569 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
4570 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
4574 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
4576 <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
4580 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
4582 <!--
4585 -->
4592 <!-- if set to SINGLE, only use 1 concurrent wave on each SP -->
4594 <!--
4597 - used (half): 0-15 68-179 (cnt=128, max=179)
4598 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
4602 - used (merged): 0-191 (cnt=192, max=191)
4607 -->
4608 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
4609 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
4610 <!-- could it be a low bit of branchstack? -->
4612 <!-- seems to be nesting level for flow control:.. -->
4613 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
4617 <!--
4620 -->
4627 <!--
4630 -->
4631 <bitfield name="NTEX" low="9" high="16" type="uint"/>
4632 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
4633 <bitfield name="NIBO" low="22" high="28" type="uint"/>
4637 <!-- # of VS outputs including pos/psize -->
4638 <bitfield name="OUT" low="0" high="5" type="uint"/>
4639 <!-- FLAGS_REGID only for GS -->
4640 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
4644 <!--
4647 -->
4649 <!--
4650 Creates a separate preamble-only thread?
4653 - Only shared, a1, and consts regs could be used
4655 - No cat5/cat6, only stc/ldc variants are working;
4656 - Values writen to shared regs are not accessible by the rest
4658 - Instructions before shps are also considered to be a part of
4663 -->
4666 <!-- bitmask of true/false conditions for VS brac.N instructions,
4667 bit N corresponds to brac.N -->
4669 <!-- # of VS outputs including pos/psize -->
4673 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4674 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4675 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4676 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4679 <!--
4685 -->
4688 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4689 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4690 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4691 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4696 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
4699 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31">
4713 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
4719 - stp/ldp offset
4720 - fiber id
4721 - wavefront id (a swizzled version of what "getwid" returns)
4722 - SP ID (the same as what "getspid" returns)
4725 TOTALPVTMEMSIZE. In the per-wave layout, the
4728 - offset % 4 (offset within dword)
4729 - fiber id
4730 - offset / 4
4731 - wavefront id
4732 - SP ID
4736 wavefront). In the per-fiber layout, the indices
4739 - offset
4740 - fiber id % 4
4741 - wavefront id
4742 - fiber id / 4
4743 - SP ID
4749 with per-fiber layout. The blob will fall back
4750 to per-wave instead.
4760 stack seems to be after all the normal per-SP private
4763 <bitfield name="OFFSET" low="0" high="18" shr="11"/>
4771 <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4773 <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4775 <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4778 <!-- There is no mergedregs bit, that comes from the VS. -->
4781 <!--
4786 -->
4787 <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>
4790 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4796 <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4798 <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4800 <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4803 <!-- There is no mergedregs bit, that comes from the VS. -->
4808 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4812 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4813 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4814 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4815 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4820 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4821 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4822 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4823 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4827 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4833 <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4835 <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4837 <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4840 <!-- There is no mergedregs bit, that comes from the VS. -->
4843 <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">
4848 size less than 63 - size
4849 size of 63 (?) or 64 - 63
4850 size greater than 64 - 64
4852 What to program when the size is 61-63 is a guess, but
4859 <!-- TODO: exact same layout as 0xa802-0xa81a -->
4863 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4864 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
4865 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
4866 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
4872 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4873 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
4874 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
4875 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
4879 <!-- TODO: exact same layout as 0xa81b-0xa825 -->
4885 <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4887 <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4889 <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4900 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
4912 <!-- note: vk blob uses bit24 -->
4934 <!-- per-mrt enable bit -->
4935 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
4941 <!-- Same as RB_SRGB_CNTL -->
4952 <bitfield name="RT0" low="0" high="3"/>
4953 <bitfield name="RT1" low="4" high="7"/>
4954 <bitfield name="RT2" low="8" high="11"/>
4955 <bitfield name="RT3" low="12" high="15"/>
4956 <bitfield name="RT4" low="16" high="19"/>
4957 <bitfield name="RT5" low="20" high="23"/>
4958 <bitfield name="RT6" low="24" high="27"/>
4959 <bitfield name="RT7" low="28" high="31"/>
4963 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
4964 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
4965 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
4968 <bitfield name="MRT" low="0" high="3" type="uint"/>
4974 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
4981 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
4989 <bitfield name="COUNT" low="0" high="2" type="uint"/>
5001 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/>
5002 <!-- Blob never uses it -->
5003 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/>
5007 <bitfield name="SRC" low="0" high="6" type="uint"/>
5008 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
5009 <bitfield name="TEX_ID" low="11" high="15" type="uint"/>
5010 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
5011 <bitfield name="WRMASK" low="22" high="25" type="hex"/>
5016 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/>
5019 …<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit…
5020 <reg32 offset="0" name="CMD" variants="A7XX-">
5021 <bitfield name="SRC" low="0" high="6" type="uint"/>
5022 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/>
5023 <bitfield name="TEX_ID" low="10" high="12" type="uint"/>
5024 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/>
5025 <bitfield name="WRMASK" low="19" high="22" type="hex"/>
5028 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/>
5033 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
5034 <bitfield name="TEX_ID" low="16" high="31" type="uint"/>
5037 <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
5038 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
5041 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
5048 <!-- seems to make SP use less concurrent threads when possible? -->
5050 <!-- has a small impact on performance, not clear what it does -->
5056 <!-- set for compute shaders -->
5058 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
5060 If 0 - all 32k of shared storage is enabled, otherwise
5064 64k (and has 36k of storage on A640 - reads between 36k-64k
5069 <!-- always 1 ? -->
5078 <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>
5080 <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>
5082 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
5083 <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
5085 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 -->
5087 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5088 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
5089 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
5090 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
5092 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 -->
5094 <!-- gl_LocalInvocationIndex -->
5095 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5096 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5097 one of those 6 "SP cores" -->
5099 <!-- Must match SP_CS_CTRL -->
5101 <!-- 1 thread per wave (ignored if bit9 set) -->
5105 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
5106 <!-- gl_LocalInvocationIndex -->
5107 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5108 <!-- Must match SP_CS_CTRL -->
5110 <!-- 1 thread per wave (would hang if THREAD128 is also set) -->
5113 <!-- Affects getone. If enabled, getone sometimes executed 1? less times
5115 -->
5119 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 -->
5137 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5138 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5141 …<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cm…
5142 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5143 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5144 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5148 <!--
5150 -->
5152 <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
5154 <!-- Correlated with avgs/uvgs usage in FS -->
5155 <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
5157 <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
5160 <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
5173 <bitfield name="RT0" low="0" high="3"/>
5174 <bitfield name="RT1" low="4" high="7"/>
5175 <bitfield name="RT2" low="8" high="11"/>
5176 <bitfield name="RT3" low="12" high="15"/>
5177 <bitfield name="RT4" low="16" high="19"/>
5178 <bitfield name="RT5" low="20" high="23"/>
5179 <bitfield name="RT6" low="24" high="27"/>
5180 <bitfield name="RT7" low="28" high="31"/>
5185 <!--
5188 out-of-bounds isam/isamm. GL and Vulkan robustness require us to
5189 return 0 on out-of-bound textureFetch().
5190 -->
5197 <!--
5199 load a 32-bit value (so hc0.y loads the same value as c0.y)
5204 -->
5206 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/>
5207 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS -->
5210 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
5211 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
5214 <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
5218 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5219 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5222 …<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_bl…
5223 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5224 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5225 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5229 <!--
5232 -->
5234 <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
5236 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
5242 <!-- looks like HW only cares about the base type of this format,
5243 which matches the ifmt? -->
5244 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/>
5245 <!-- set when ifmt is R2D_UNORM8_SRGB -->
5247 <!-- some sort of channel mask, not sure what it is for -->
5248 <bitfield name="MASK" low="12" high="15"/>
5252 …<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage…
5257 <!-- TODO: valid bits 0x3c3f, see kernel -->
5264 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
5265 <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
5266 <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
5267 <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
5270 <!-- some perfcntrs are affected by a per-stage enable bit
5272 TODO: verify position of HS/DS/GS bits -->
5281 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
5282 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
5283 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
5284 <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
5285 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
5286 <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/>
5287 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/>
5288 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/>
5289 <bitfield name="USPTP" low="4" high="7"/>
5290 <bitfield name="SPTP" low="0" high="3"/>
5292 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
5293 <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
5294 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
5295 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
5296 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
5299 <!--
5303 -->
5305 <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
5306 <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
5311 <!-- could be all the stuff below here is actually TPL1?? -->
5314 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5315 <bitfield name="UNK2" low="2" high="3"/>
5318 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5322 <!-- looks to work in the same way as a5xx: -->
5329 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
5330 <bitfield name="UNK3" low="2" high="7"/>
5332 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
5334 <!--
5338 -->
5341 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5342 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5346 <bitfield name="UNK0" low="0" high="8"/>
5347 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
5350 …<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usag…
5352 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5353 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5355 …<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_bl…
5357 <bitfield name="UNK0" low="0" high="8"/>
5358 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/>
5361 <!-- planes for NV12, etc. (TODO: not tested) -->
5363 …<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" varia…
5366 <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
5367 …2 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="…
5368 <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
5371 …<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" varian…
5373 …<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage=…
5374 …2 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A…
5376 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
5377 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
5378 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
5379 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
5382 <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
5383 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
5384 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
5385 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
5387 <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
5388 …<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"…
5390 <!-- always 0x100000 or 0x1000000? -->
5391 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
5394 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set
5395 and if other blit is done without it - UBWC image may be copied incorrectly.
5396 -->
5401 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/>
5402 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b -->
5404 <bitfield name="UNK6" low="6" high="7"/>
5406 …0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- a…
5408 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>
5409 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>
5410 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>
5411 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>
5412 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>
5414 …<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage…
5415 …<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage…
5416 …<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage…
5417 …<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage…
5418 …<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage…
5423 <!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
5426 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
5428 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/>
5436 …<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5437 …<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5438 …<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5439 …<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5441 <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
5442 <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG -->
5446 <!-- Always 0 -->
5447 <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
5449 <!-- Used in VK_KHR_fragment_shading_rate -->
5450 <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
5452 <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
5453 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
5454 <!-- UNK8 is set on a730/a740 -->
5456 <!-- UNK9 is set on a750 -->
5466 <!-- must match SP_FS_CTRL -->
5469 <bitfield name="UNK2" low="2" high="11"/>
5472 <!-- register loaded with position (bary.f) -->
5473 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
5474 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
5475 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
5476 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
5479 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
5480 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
5481 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
5482 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
5485 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
5486 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/>
5490 …b981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob -->
5491 <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">
5492 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the
5494 the hardware will simply emit smaller waves when it runs out of space. -->
5495 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5498 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5499 <!-- SAMPLEID is loaded into a half-precision register: -->
5500 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
5501 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
5502 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
5508 …<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp…
5509 <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
5510 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5512 <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
5513 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5514 <!-- SAMPLEID is loaded into a half-precision register: -->
5515 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
5516 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
5517 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/>
5519 …<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" u…
5520 …<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" u…
5521 …<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" u…
5522 <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
5524 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5526 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5527 <!-- localsize is value minus one: -->
5528 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5529 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5530 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5533 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5536 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5539 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5542 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5545 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5548 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5551 <!-- these are all vec3. first 3 need to be high regs
5554 -->
5555 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5556 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/>
5557 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/>
5558 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
5561 <!-- gl_LocalInvocationIndex -->
5562 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5563 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only
5564 one of those 6 "SP cores" -->
5566 <!-- Must match SP_CS_CTRL -->
5568 <!-- 1 thread per wave (ignored if bit9 set) -->
5571 <!--note: vulkan blob doesn't use these -->
5576 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) -->
5577 <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
5578 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5579 <!-- localsize is value minus one: -->
5580 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5581 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5582 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5584 <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
5585 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5587 <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
5588 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5590 <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
5591 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5593 <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
5594 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5596 <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
5597 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5599 <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
5600 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5602 <!--note: vulkan blob doesn't use these -->
5603 <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
5604 <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
5605 <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
5614 <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
5615 <!-- gl_LocalInvocationIndex -->
5616 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5617 <!-- Must match SP_CS_CTRL -->
5622 <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/>
5625 <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
5626 <!-- localsize is value minus one: -->
5627 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
5628 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
5629 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
5636 <!-- mirror of SP_CS_BINDLESS_BASE -->
5639 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5640 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5644 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? -->
5646 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
5648 <!-- always 1 ? -->
5653 <bitfield name="STATE_ID" low="0" high="7"/>
5657 <bitfield name="STATE_ID" low="0" high="7"/>
5661 <!-- I think only the low bit is actually used? -->
5662 <bitfield name="STATE_ID" low="16" high="23"/>
5663 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5673 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5684 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 -->
5688 <!-- SS6_BINDLESS: one bit per bindless base -->
5689 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/>
5690 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/>
5693 <reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">
5694 <bitfield name="STATE_ID" low="0" high="7"/>
5697 <reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">
5698 <bitfield name="STATE_ID" low="0" high="7"/>
5701 <reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">
5702 <bitfield name="STATE_ID" low="16" high="23"/>
5703 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5706 <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
5713 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers -->
5724 <!-- SS6_BINDLESS: one bit per bindless base -->
5725 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/>
5726 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/>
5730 …<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5732 <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
5740 c504-c511 in each stage. Both VS and FS shared consts
5756 <!-- mirror of SP_BINDLESS_BASE -->
5759 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5760 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/>
5765 <bitfield name="STATE_ID" low="8" high="15"/>
5766 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5769 …xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 -->
5770 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
5773 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
5776 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
5779 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
5781 <!-- Don't know if these are SP, always 0 -->
5782 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
5783 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
5784 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
5786 <!--
5789 - write EVENT_CMD pipe register
5790 - write CP_EVENT_START
5791 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD
5792 - write PC_EVENT_CMD with event or PC_DRAW_CMD
5793 - write HLSQ_EVENT_CMD(CONTEXT_DONE)
5794 - write PC_EVENT_CMD(CONTEXT_DONE)
5795 - write CP_EVENT_END
5797 -->
5799 <bitfield name="STATE_ID" low="0" high="7"/>
5802 <bitfield name="STATE_ID" low="0" high="7"/>
5805 <bitfield name="STATE_ID" low="0" high="7"/>
5808 <bitfield name="STATE_ID" low="0" high="7"/>
5812 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
5815 <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
5819 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only -->
5821 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
5828 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
5843 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
5844 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
5845 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
5846 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
5847 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
5848 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
5849 …<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits fo…
5855 [-1, 1] if the format is snorm, *after*
5859 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
5863 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
5864 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
5867 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
5869 <bitfield name="BCOLOR" low="7" high="31"/>
5876 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
5884 <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
5892 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
5894 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
5895 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
5896 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
5897 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
5898 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
5899 <!-- overlaps with MIPLVLS -->
5902 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
5903 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/>
5904 <!--
5908 -->
5909 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
5912 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
5913 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
5914 <bitfield name="MUTABLEEN" pos="31" type="boolean" variants="A7XX-"/>
5917 <!--
5920 -->
5922 <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/>
5923 <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/>
5925 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
5926 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
5928 <bitfield name="PITCH" low="7" high="28" type="uint"/>
5929 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/>
5932 <!--
5937 -->
5938 <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
5939 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
5940 <!--
5944 -->
5948 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled)
5949 the address of the non-flag base buffer is determined automatically,
5951 -->
5953 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
5956 <bitfield name="BASE_HI" low="0" high="16"/>
5957 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
5960 <!-- overlaps with PLANE_PITCH -->
5961 <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
5962 <!-- pitch for plane 2 / plane 3 -->
5963 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/>
5965 <!-- 7/8 is plane 2 address for planar formats -->
5967 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
5970 <bitfield name="FLAG_HI" low="0" high="16"/>
5972 <!-- 9/10 is plane 3 address for planar formats -->
5974 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
5977 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
5978 <!-- log2 size of the first level, required for mipmapping -->
5979 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/>
5980 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/>
5991 <bitfield name="BASE_LO" low="0" high="31"/>
5994 <bitfield name="BASE_HI" low="0" high="16"/>
5995 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units -->
6034 <bitfield high="7" low="0" name="PING_INDEX"/>
6035 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
6041 <bitfield high="5" low="0" name="TRACEEN"/>
6042 <bitfield high="14" low="12" name="GRANU"/>
6043 <bitfield high="31" low="28" name="SEGT"/>
6046 <bitfield high="27" low="24" name="ENABLE"/>
6057 <bitfield high="3" low="0" name="BYTEL0"/>
6058 <bitfield high="7" low="4" name="BYTEL1"/>
6059 <bitfield high="11" low="8" name="BYTEL2"/>
6060 <bitfield high="15" low="12" name="BYTEL3"/>
6061 <bitfield high="19" low="16" name="BYTEL4"/>
6062 <bitfield high="23" low="20" name="BYTEL5"/>
6063 <bitfield high="27" low="24" name="BYTEL6"/>
6064 <bitfield high="31" low="28" name="BYTEL7"/>
6067 <bitfield high="3" low="0" name="BYTEL8"/>
6068 <bitfield high="7" low="4" name="BYTEL9"/>
6069 <bitfield high="11" low="8" name="BYTEL10"/>
6070 <bitfield high="15" low="12" name="BYTEL11"/>
6071 <bitfield high="19" low="16" name="BYTEL12"/>
6072 <bitfield high="23" low="20" name="BYTEL13"/>
6073 <bitfield high="27" low="24" name="BYTEL14"/>
6074 <bitfield high="31" low="28" name="BYTEL15"/>
6084 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
6085 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">