Lines Matching +full:0 +full:x9880

25 	<value name="TILE6_LINEAR" value="0"/>
31 	<value value="0x02" name="FMT6_A8_UNORM"/>
32 	<value value="0x03" name="FMT6_8_UNORM"/>
33 	<value value="0x04" name="FMT6_8_SNORM"/>
34 	<value value="0x05" name="FMT6_8_UINT"/>
35 	<value value="0x06" name="FMT6_8_SINT"/>
37 	<value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
38 	<value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
39 	<value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
40 	<value value="0x0e" name="FMT6_5_6_5_UNORM"/>
42 	<value value="0x0f" name="FMT6_8_8_UNORM"/>
43 	<value value="0x10" name="FMT6_8_8_SNORM"/>
44 	<value value="0x11" name="FMT6_8_8_UINT"/>
45 	<value value="0x12" name="FMT6_8_8_SINT"/>
46 	<value value="0x13" name="FMT6_L8_A8_UNORM"/>
48 	<value value="0x15" name="FMT6_16_UNORM"/>
49 	<value value="0x16" name="FMT6_16_SNORM"/>
50 	<value value="0x17" name="FMT6_16_FLOAT"/>
51 	<value value="0x18" name="FMT6_16_UINT"/>
52 	<value value="0x19" name="FMT6_16_SINT"/>
54 	<value value="0x21" name="FMT6_8_8_8_UNORM"/>
55 	<value value="0x22" name="FMT6_8_8_8_SNORM"/>
56 	<value value="0x23" name="FMT6_8_8_8_UINT"/>
57 	<value value="0x24" name="FMT6_8_8_8_SINT"/>
59 	<value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
60 	<value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
61 	<value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
62 	<value value="0x33" name="FMT6_8_8_8_8_UINT"/>
63 	<value value="0x34" name="FMT6_8_8_8_8_SINT"/>
65 	<value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
67 	<value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
68 	<value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
69 	<value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
70 	<value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
71 	<value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
73 	<value value="0x42" name="FMT6_11_11_10_FLOAT"/>
75 	<value value="0x43" name="FMT6_16_16_UNORM"/>
76 	<value value="0x44" name="FMT6_16_16_SNORM"/>
77 	<value value="0x45" name="FMT6_16_16_FLOAT"/>
78 	<value value="0x46" name="FMT6_16_16_UINT"/>
79 	<value value="0x47" name="FMT6_16_16_SINT"/>
81 	<value value="0x48" name="FMT6_32_UNORM"/>
82 	<value value="0x49" name="FMT6_32_SNORM"/>
83 	<value value="0x4a" name="FMT6_32_FLOAT"/>
84 	<value value="0x4b" name="FMT6_32_UINT"/>
85 	<value value="0x4c" name="FMT6_32_SINT"/>
86 	<value value="0x4d" name="FMT6_32_FIXED"/>
88 	<value value="0x58" name="FMT6_16_16_16_UNORM"/>
89 	<value value="0x59" name="FMT6_16_16_16_SNORM"/>
90 	<value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
91 	<value value="0x5b" name="FMT6_16_16_16_UINT"/>
92 	<value value="0x5c" name="FMT6_16_16_16_SINT"/>
94 	<value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
95 	<value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
96 	<value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
97 	<value value="0x63" name="FMT6_16_16_16_16_UINT"/>
98 	<value value="0x64" name="FMT6_16_16_16_16_SINT"/>
100 	<value value="0x65" name="FMT6_32_32_UNORM"/>
101 	<value value="0x66" name="FMT6_32_32_SNORM"/>
102 	<value value="0x67" name="FMT6_32_32_FLOAT"/>
103 	<value value="0x68" name="FMT6_32_32_UINT"/>
104 	<value value="0x69" name="FMT6_32_32_SINT"/>
105 	<value value="0x6a" name="FMT6_32_32_FIXED"/>
107 	<value value="0x70" name="FMT6_32_32_32_UNORM"/>
108 	<value value="0x71" name="FMT6_32_32_32_SNORM"/>
109 	<value value="0x72" name="FMT6_32_32_32_UINT"/>
110 	<value value="0x73" name="FMT6_32_32_32_SINT"/>
111 	<value value="0x74" name="FMT6_32_32_32_FLOAT"/>
112 	<value value="0x75" name="FMT6_32_32_32_FIXED"/>
114 	<value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
115 	<value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
116 	<value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
117 	<value value="0x83" name="FMT6_32_32_32_32_UINT"/>
118 	<value value="0x84" name="FMT6_32_32_32_32_SINT"/>
119 	<value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
121 	<value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY -->
122 	<value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV -->
123 	<value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 -->
124 	<value value="0x8f" name="FMT6_NV21"/>
125 	<value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 -->
127 	<value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
132 	<value value="0x94" name="FMT6_NV12_Y"/>
133 	<value value="0x95" name="FMT6_NV12_UV"/>
134 	<value value="0x96" name="FMT6_NV12_VU"/>
135 	<value value="0x97" name="FMT6_NV12_4R"/>
136 	<value value="0x98" name="FMT6_NV12_4R_Y"/>
137 	<value value="0x99" name="FMT6_NV12_4R_UV"/>
138 	<value value="0x9a" name="FMT6_P010"/>
139 	<value value="0x9b" name="FMT6_P010_Y"/>
140 	<value value="0x9c" name="FMT6_P010_UV"/>
141 	<value value="0x9d" name="FMT6_TP10"/>
142 	<value value="0x9e" name="FMT6_TP10_Y"/>
143 	<value value="0x9f" name="FMT6_TP10_UV"/>
145 	<value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
147 	<value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
148 	<value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
149 	<value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
150 	<value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
151 	<value value="0xaf" name="FMT6_ETC1"/>
152 	<value value="0xb0" name="FMT6_ETC2_RGB8"/>
153 	<value value="0xb1" name="FMT6_ETC2_RGBA8"/>
154 	<value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
155 	<value value="0xb3" name="FMT6_DXT1"/>
156 	<value value="0xb4" name="FMT6_DXT3"/>
157 	<value value="0xb5" name="FMT6_DXT5"/>
158 	<value value="0xb7" name="FMT6_RGTC1_UNORM"/>
159 	<value value="0xb8" name="FMT6_RGTC1_SNORM"/>
160 	<value value="0xbb" name="FMT6_RGTC2_UNORM"/>
161 	<value value="0xbc" name="FMT6_RGTC2_SNORM"/>
162 	<value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
163 	<value value="0xbf" name="FMT6_BPTC_FLOAT"/>
164 	<value value="0xc0" name="FMT6_BPTC"/>
165 	<value value="0xc1" name="FMT6_ASTC_4x4"/>
166 	<value value="0xc2" name="FMT6_ASTC_5x4"/>
167 	<value value="0xc3" name="FMT6_ASTC_5x5"/>
168 	<value value="0xc4" name="FMT6_ASTC_6x5"/>
169 	<value value="0xc5" name="FMT6_ASTC_6x6"/>
170 	<value value="0xc6" name="FMT6_ASTC_8x5"/>
171 	<value value="0xc7" name="FMT6_ASTC_8x6"/>
172 	<value value="0xc8" name="FMT6_ASTC_8x8"/>
173 	<value value="0xc9" name="FMT6_ASTC_10x5"/>
174 	<value value="0xca" name="FMT6_ASTC_10x6"/>
175 	<value value="0xcb" name="FMT6_ASTC_10x8"/>
176 	<value value="0xcc" name="FMT6_ASTC_10x10"/>
177 	<value value="0xcd" name="FMT6_ASTC_12x10"/>
178 	<value value="0xce" name="FMT6_ASTC_12x12"/>
181 	<value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/>
184 	<value value="0xff" name="FMT6_NONE"/>
196 	<value name="DEPTH6_NONE" value="0"/>
203 	<bitfield name="BASE_ADDR" low="0" high="17"/>
209 	<value value="0x9" name="A6XX_TP0_TMO_DATA"/>
210 	<value value="0xa" name="A6XX_TP0_SMO_DATA"/>
211 	<value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
212 	<value value="0x19" name="A6XX_TP1_TMO_DATA"/>
213 	<value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
214 	<value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
215 	<value value="0x29" name="A6XX_SP_INST_DATA"/>
216 	<value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
217 	<value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
218 	<value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
219 	<value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
220 	<value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
221 	<value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
222 	<value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
223 	<value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
224 	<value value="0x32" name="A6XX_SP_UAV_DATA"/>
225 	<value value="0x33" name="A6XX_SP_INST_TAG"/>
226 	<value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
227 	<value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
228 	<value value="0x36" name="A6XX_SP_SMO_TAG"/>
229 	<value value="0x37" name="A6XX_SP_STATE_DATA"/>
230 	<value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
231 	<value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
232 	<value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
233 	<value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
234 	<value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
235 	<value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
236 	<value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
237 	<value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
238 	<value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
239 	<value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
240 	<value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
241 	<value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
242 	<value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
243 	<value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
244 	<value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
245 	<value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
246 	<value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
247 	<value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
248 	<value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
249 	<value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
250 	<value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
251 	<value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
252 	<value value="0x70" name="A6XX_SP_LB_6_DATA"/>
253 	<value value="0x71" name="A6XX_SP_LB_7_DATA"/>
254 	<value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/>
258 	<value value="0" name="A7XX_TP0_NCTX_REG"/>
337 	<value value="0x1" name="A6XX_DBGBUS_CP"/>
338 	<value value="0x2" name="A6XX_DBGBUS_RBBM"/>
339 	<value value="0x3" name="A6XX_DBGBUS_VBIF"/>
340 	<value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
341 	<value value="0x5" name="A6XX_DBGBUS_UCHE"/>
342 	<value value="0x6" name="A6XX_DBGBUS_DPM"/>
343 	<value value="0x7" name="A6XX_DBGBUS_TESS"/>
344 	<value value="0x8" name="A6XX_DBGBUS_PC"/>
345 	<value value="0x9" name="A6XX_DBGBUS_VFDP"/>
346 	<value value="0xa" name="A6XX_DBGBUS_VPC"/>
347 	<value value="0xb" name="A6XX_DBGBUS_TSE"/>
348 	<value value="0xc" name="A6XX_DBGBUS_RAS"/>
349 	<value value="0xd" name="A6XX_DBGBUS_VSC"/>
350 	<value value="0xe" name="A6XX_DBGBUS_COM"/>
351 	<value value="0x10" name="A6XX_DBGBUS_LRZ"/>
352 	<value value="0x11" name="A6XX_DBGBUS_A2D"/>
353 	<value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
354 	<value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
355 	<value value="0x14" name="A6XX_DBGBUS_RBP"/>
356 	<value value="0x15" name="A6XX_DBGBUS_DCS"/>
357 	<value value="0x16" name="A6XX_DBGBUS_DBGC"/>
358 	<value value="0x17" name="A6XX_DBGBUS_CX"/>
359 	<value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
360 	<value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
361 	<value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
362 	<value value="0x1d" name="A6XX_DBGBUS_GPC"/>
363 	<value value="0x1e" name="A6XX_DBGBUS_LARC"/>
364 	<value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
365 	<value value="0x20" name="A6XX_DBGBUS_RB_0"/>
366 	<value value="0x21" name="A6XX_DBGBUS_RB_1"/>
367 	<value value="0x22" name="A6XX_DBGBUS_RB_2"/>
368 	<value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
369 	<value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
370 	<value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
371 	<value value="0x2a" name="A6XX_DBGBUS_CCU_2"/>
372 	<value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
373 	<value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
374 	<value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
375 	<value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
376 	<value value="0x3c" name="A6XX_DBGBUS_VFD_4"/>
377 	<value value="0x3d" name="A6XX_DBGBUS_VFD_5"/>
378 	<value value="0x40" name="A6XX_DBGBUS_SP_0"/>
379 	<value value="0x41" name="A6XX_DBGBUS_SP_1"/>
380 	<value value="0x42" name="A6XX_DBGBUS_SP_2"/>
381 	<value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
382 	<value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
383 	<value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
384 	<value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
385 	<value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/>
386 	<value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/>
387 	<value value="0x58" name="A6XX_DBGBUS_SPTP_0"/>
388 	<value value="0x59" name="A6XX_DBGBUS_SPTP_1"/>
389 	<value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/>
390 	<value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/>
391 	<value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/>
392 	<value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/>
396 	<value value="0" name="A7XX_HLSQ_STATE"/>
404 	<value value="0" name="A7XX_PIPE_NONE"/>
411 	<value value="0" name="A7XX_CLUSTER_NONE"/>
531 	<value value="0" name="PERF_CP_ALWAYS_COUNT"/>
584 	<value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
601 	<value value="0" name="PERF_PC_BUSY_CYCLES"/>
646 	<value value="0" name="PERF_VFD_BUSY_CYCLES"/>
672 	<value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
696 	<value value="0" name="PERF_VPC_BUSY_CYCLES"/>
727 	<value value="0" name="PERF_TSE_BUSY_CYCLES"/>
750 	<value value="0" name="PERF_RAS_BUSY_CYCLES"/>
766 	<value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
809 	<value value="0" name="PERF_TP_BUSY_CYCLES"/>
869 	<value value="0" name="PERF_SP_BUSY_CYCLES"/>
957 	<value value="0" name="PERF_RB_BUSY_CYCLES"/>
1008 	<value value="0" name="PERF_VSC_BUSY_CYCLES"/>
1016 	<value value="0" name="PERF_CCU_BUSY_CYCLES"/>
1048 	<value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
1079 	<value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
1128  8b unorm:  10 (sometimes 0, is the high bit part of something else?)
1139 	<value value="0x10" name="R2D_UNORM8"/>
1140 	<value value="0x7"  name="R2D_INT32"/>
1141 	<value value="0x6"  name="R2D_INT16"/>
1142 	<value value="0x5"  name="R2D_INT8"/>
1143 	<value value="0x4"  name="R2D_FLOAT32"/>
1144 	<value value="0x3"  name="R2D_FLOAT16"/>
1145 	<value value="0x1"  name="R2D_UNORM8_SRGB"/>
1146 	<value value="0x0"  name="R2D_RAW"/>
1151 	<value value="0x0" name="A6XX_EARLY_Z"/>
1153 	<value value="0x1" name="A6XX_LATE_Z"/>
1184 	<value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
1186 	<value value="0x3" name="A6XX_INVALID_ZTEST"/>
1190 	<value value="0x0" name="TESS_EQUAL"/>
1191 	<value value="0x2" name="TESS_FRACTIONAL_ODD"/>
1192 	<value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
1195 	<value value="0x0" name="TESS_POINTS"/>
1196 	<value value="0x1" name="TESS_LINES"/>
1197 	<value value="0x2" name="TESS_CW_TRIS"/>
1198 	<value value="0x3" name="TESS_CCW_TRIS"/>
1202 	<value value="0" name="A7XX_PERF_CP_ALWAYS_COUNT"/>
1286 	<value value="0" name="A7XX_PERF_RBBM_ALWAYS_COUNT"/>
1303 	<value value="0" name="A7XX_PERF_PC_BUSY_CYCLES"/>
1358 	<value value="0" name="A7XX_PERF_VFD_BUSY_CYCLES"/>
1386 	<value value="0" name="A7XX_PERF_HLSQ_BUSY_CYCLES"/>
1447 	<value value="0" name="A7XX_PERF_VPC_BUSY_CYCLES"/>
1494 	<value value="0" name="A7XX_PERF_TSE_BUSY_CYCLES"/>
1517 	<value value="0" name="A7XX_PERF_RAS_BUSY_CYCLES"/>
1551 	<value value="0" name="A7XX_PERF_UCHE_BUSY_CYCLES"/>
1613 	<value value="0" name="A7XX_PERF_TP_BUSY_CYCLES"/>
1749 	<value value="0" name="A7XX_PERF_SP_BUSY_CYCLES"/>
1903 	<value value="0" name="A7XX_PERF_RB_BUSY_CYCLES"/>
1960 	<value value="0" name="A7XX_PERF_VSC_BUSY_CYCLES"/>
1968 	<value value="0" name="A7XX_PERF_CCU_BUSY_CYCLES"/>
1994 	<value value="0" name="A7XX_PERF_LRZ_BUSY_CYCLES"/>
2025 	<value value="0" name="A7XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/>
2078 	<value value="0" name="A7XX_PERF_GBIF_RESERVED_0"/>
2162 	<value value="0" name="A7XX_PERF_UFC_BUSY_CYCLES"/>
2224 		<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
2262 		<bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
2281 	<reg64 offset="0x0800" name="CP_RB_BASE"/>
2282 	<reg32 offset="0x0802" name="CP_RB_CNTL"/>
2283 	<reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
2284 	<reg32 offset="0x0806" name="CP_RB_RPTR"/>
2285 	<reg32 offset="0x0807" name="CP_RB_WPTR"/>
2286 	<reg32 offset="0x0808" name="CP_SQE_CNTL"/>
2287 	<reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
2288 		<bitfield name="IFPC" pos="0" type="boolean"/>
2290 	<reg32 offset="0x0821" name="CP_HW_FAULT"/>
2291 	<reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/>
2292 	<reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
2293 	<reg32 offset="0x0825" name="CP_STATUS_1"/>
2294 	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/>
2295 	<reg32 offset="0x0840" name="CP_MISC_CNTL"/>
2296 	<reg32 offset="0x0844" name="CP_APRIV_CNTL">
2311 		<bitfield pos="0" name="ICACHE" type="boolean"/>
2314 	<reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/>
2316 	<reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
2323 		<bitfield name="MRB_START" low="0" high="7" shr="2"/>
2328 	<reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
2336 					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
2337 					kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
2340 		<bitfield name="SDS_START" low="0" high="8" shr="2"/>
2344 	<reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
2345 	<reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
2346 	<reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2347 	<reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
2348 	<reg32 offset="0x084F" name="CP_PROTECT_CNTL">
2351 		<bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/>
2354 	<array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
2355 		<reg32 offset="0x0" name="REG" type="uint"/>
2357 	<array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
2358 		<reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
2361 	<reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL">
2362 		<bitfield name="STOP" pos="0" type="boolean"/>
2367 	<reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/>
2368 	<reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/>
2369 	<reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/>
2370 	<reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/>
2371 	<reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/>
2372 	<array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/>
2373 	<array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/>
2374 	<reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/>
2375 	<reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
2376 	<reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
2377 	<reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
2378 	<reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
2379 	<reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
2380 	<reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
2381 	<reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
2382 	<reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
2383 	<reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
2384 	<reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
2385 	<reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
2386 	<reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
2387 	<reg64 offset="0x0928" name="CP_IB1_BASE"/>
2388 	<reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
2389 	<reg64 offset="0x092B" name="CP_IB2_BASE"/>
2390 	<reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
2392 	<reg64 offset="0x092e" name="CP_SDS_BASE"/>
2393 	<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
2395 	<reg64 offset="0x0931" name="CP_MRB_BASE"/>
2396 	<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
2401 	<reg64 offset="0x0934" name="CP_VSD_BASE"/>
2404 		<bitfield name="RPTR" low="0" high="9"/>
2407 	<reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/>
2408 	<reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/>
2409 	<reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/>
2410 	<reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/>
2411 	<reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/>
2412 	<reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/>
2414 	<reg32 offset="0x0943" name="CP_IB1_DWORDS"/>
2415 	<reg32 offset="0x0944" name="CP_IB2_DWORDS"/>
2416 	<reg32 offset="0x0945" name="CP_SDS_DWORDS"/>
2417 	<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
2418 	<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
2420 	<reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB">
2424 	<reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1">
2428 	<reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2">
2432 	<reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS">
2436 	<reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB">
2440 	<reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD">
2450 	<reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
2451 	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>
2452 	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
2453 	<reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
2454 	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/>
2455 	<reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/>
2457 	<reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/>
2458 	<reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/>
2459 	<reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/>
2460 	<reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/>
2461 	<reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/>
2462 	<reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/>
2463 	<reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/>
2464 	<reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/>
2465 	<reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/>
2466 	<reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/>
2467 	<reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/>
2468 	<reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/>
2469 	<reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/>
2471 	<reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/>
2472 	<reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/>
2473 	<reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/>
2474 	<reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/>
2476 	<reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/>
2477 	<reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/>
2478 	<reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/>
2479 	<reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/>
2480 	<reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/>
2481 	<reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/>
2482 	<reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/>
2484 	<reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/>
2485 	<reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/>
2486 	<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
2487 	<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
2488 	<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
2489 	<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
2490 	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
2492 	<reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/>
2493 	<reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/>
2494 	<reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/>
2496 	<reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/>
2497 	<reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/>
2498 	<reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/>
2499 	<reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/>
2500 	<reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/>
2501 	<reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/>
2502 	<reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/>
2503 	<reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/>
2504 	<reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/>
2505 	<reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/>
2506 	<reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/>
2507 	<reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/>
2509 	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2510 	<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
2511 	<reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
2512 	<reg32 offset="0x0210" name="RBBM_STATUS">
2536 		<bitfield pos="0"  name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
2538 	<reg32 offset="0x0211" name="RBBM_STATUS1"/>
2539 	<reg32 offset="0x0212" name="RBBM_STATUS2"/>
2540 	<reg32 offset="0x0213" name="RBBM_STATUS3">
2543 	<reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
2545 	<reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/>
2546 	<reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/>
2547 	<reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/>
2548 	<reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/>
2549 	<reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/>
2550 	<reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/>
2552 	<reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/>
2553 	<reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/>
2555 	<array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/>
2556 	<array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/>
2557 	<array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/>
2558 	<array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/>
2559 	<array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/>
2560 	<array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/>
2561 	<array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/>
2562 	<array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/>
2563 	<array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/>
2564 	<array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/>
2565 	<array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/>
2566 	<array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/>
2567 	<array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/>
2568 	<array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/>
2569 	<array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/>
2570 	<array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/>
2572 	<array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/>
2573 	<array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/>
2574 	<array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/>
2575 	<array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/>
2576 	<array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/>
2577 	<array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/>
2578 	<array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/>
2579 	<array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/>
2580 	<array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/>
2581 	<array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/>
2582 	<array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/>
2583 	<array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/>
2584 	<array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/>
2585 	<array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/>
2586 	<array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/>
2587 	<array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/>
2588 	<array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/>
2589 	<array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/>
2590 	<array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/>
2591 	<array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/>
2592 	<array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/>
2593 	<array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/>
2594 	<array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/>
2595 	<array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/>
2596 	<array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/>
2597 	<array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/>
2598 	<array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/>
2599 	<array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/>
2601 	<reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
2602 	<reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
2603 	<reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
2604 	<reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
2605 	<reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
2606 	<reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
2607 	<reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
2608 	<array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/>
2609 	<reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
2610 	<reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/>
2611 	<reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/>
2612 	<reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
2613 	<reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/>
2614 	<reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/>
2622 	<reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/>  <!-- vs vertices in -->
2623 	<reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
2624 	<reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/>  <!-- vs primitives out -->
2625 	<reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
2626 	<reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/>  <!-- hs vertices in -->
2627 	<reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
2628 	<reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/>  <!-- hs patches out -->
2629 	<reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
2630 	<reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/>  <!-- dss vertices in -->
2631 	<reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
2632 	<reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/>  <!-- ds primitives out -->
2633 	<reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
2634 	<reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/>  <!-- gs primitives in -->
2635 	<reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
2636 	<reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/>  <!-- gs primitives out -->
2637 	<reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
2638 	<reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/>  <!-- gs primitives out -->
2639 	<reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
2640 	<reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/>  <!-- raster primitives in -->
2641 	<reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
2642 	<reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
2643 	<reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
2645 	<reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
2646 	<reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/>
2647 	<reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
2648 	<reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
2649 	<reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2650 	<reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/>
2651 	<reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
2652 	<reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
2653 	<reg32 offset="0x00016" name="RBBM_GBIF_HALT"/>
2654 	<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/>
2655 	<reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
2656 		<bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
2659 	<reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/>
2660 	<reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/>
2661 	<reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
2662 	<reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
2663 	<reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/>
2664 	<reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/>
2665 	<reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
2666 	<reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
2667 	<reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
2668 	<reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
2669 	<reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
2670 	<reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/>
2671 	<reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
2672 	<reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
2673 	<reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
2674 	<reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
2675 	<reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
2676 	<reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
2677 	<reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
2678 	<reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
2679 	<reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
2680 	<reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
2681 	<reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
2682 	<reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
2683 	<reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
2684 	<reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
2685 	<reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
2686 	<reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
2687 	<reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
2688 	<reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
2689 	<reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
2690 	<reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
2691 	<reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
2692 	<reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
2693 	<reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
2694 	<reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
2695 	<reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
2696 	<reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
2697 	<reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
2698 	<reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
2699 	<reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
2700 	<reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
2701 	<reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
2702 	<reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
2703 	<reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
2704 	<reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
2705 	<reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
2706 	<reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
2707 	<reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
2708 	<reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
2709 	<reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
2710 	<reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
2711 	<reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
2712 	<reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
2713 	<reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
2714 	<reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
2715 	<reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
2716 	<reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
2717 	<reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
2718 	<reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
2719 	<reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
2720 	<reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
2721 	<reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
2722 	<reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
2723 	<reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
2724 	<reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
2725 	<reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
2726 	<reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
2727 	<reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
2728 	<reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
2729 	<reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
2730 	<reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
2731 	<reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
2732 	<reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
2733 	<reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
2734 	<reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
2735 	<reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
2736 	<reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
2737 	<reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
2738 	<reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
2739 	<reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
2740 	<reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
2741 	<reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
2742 	<reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
2743 	<reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
2744 	<reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
2745 	<reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
2746 	<reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
2747 	<reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
2748 	<reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
2749 	<reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
2750 	<reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
2751 	<reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
2752 	<reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
2753 	<reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
2754 	<reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
2755 	<reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
2756 	<reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
2757 	<reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
2758 	<reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
2759 	<reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
2760 	<reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
2761 	<reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
2762 	<reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
2763 	<reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
2764 	<reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
2765 	<reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
2766 	<reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
2767 	<reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
2768 	<reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
2769 	<reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
2770 	<reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
2771 	<reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
2772 	<reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
2773 	<reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
2774 	<reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
2775 	<reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
2776 	<reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
2777 	<reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
2778 	<reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/>
2779 	<reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/>
2780 	<reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
2781 	<reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
2782 	<reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
2783 	<reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-">
2784 		<bitfield name="TXDONE" pos="0" type="boolean"/>
2786 	<reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/>
2787 	<reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/>
2788 	<reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/>
2789 	<reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/>
2790 	<reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/>
2791 	<reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/>
2792 	<reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/>
2793 	<reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/>
2794 	<reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/>
2795 	<reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/>
2796 	<reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/>
2798 	<reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
2799 	<reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
2800 	<reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
2801 	<reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
2802 		<bitfield high="7" low="0" name="PING_INDEX"/>
2805 	<reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
2806 		<bitfield high="5" low="0" name="TRACEEN"/>
2810 	<reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
2813 	<reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
2814 	<reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
2815 	<reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
2816 	<reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
2817 	<reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
2818 	<reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
2819 	<reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
2820 	<reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
2821 	<reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
2822 		<bitfield high="3" low="0" name="BYTEL0"/>
2831 	<reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
2832 		<bitfield high="3" low="0" name="BYTEL8"/>
2841 	<reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
2842 	<reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
2843 	<array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/>
2844 	<reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX">
2848 		<bitfield name="BINNING" pos="0" type="boolean"/>
2850 	<reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
2851 	<reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
2852 	<reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
2853 	<reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
2854 	<reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/>
2855 	<reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/>
2856 	<reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/>
2857 	<reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/>
2858 	<reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/>
2859 	<reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/>
2860 	<reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
2861 	<reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd">
2862 		<bitfield high="7" low="0" name="PERFSEL"/>
2864 	<array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/>
2865 	<reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/>
2866 	<reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/>
2868 	<reg32 offset="0x3000" name="VBIF_VERSION"/>
2869 	<reg32 offset="0x3001" name="VBIF_CLKON">
2872 	<reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
2873 	<reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
2874 	<reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
2875 	<reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
2876 	<reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
2877 	<reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
2878 		<bitfield low="0" high="3" name="DATA_SEL"/>
2880 	<reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
2881 	<reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
2882 		<bitfield low="0" high="8" name="DATA_SEL"/>
2884 	<reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
2885 	<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
2886 	<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
2887 	<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
2888 	<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
2889 	<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
2890 	<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
2891 	<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
2892 	<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
2893 	<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
2894 	<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
2895 	<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
2896 	<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
2897 	<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
2898 	<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
2899 	<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
2900 	<reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
2901 	<reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
2902 	<reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
2903 	<reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
2904 	<reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
2905 	<reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
2907 	<reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/>
2908 	<reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
2909 	<reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
2910 	<reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
2911 	<reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
2912 	<reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
2913 	<reg32 offset="0x3c45" name="GBIF_HALT"/>
2914 	<reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
2915 	<reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
2916 	<reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/>
2917 	<reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
2918 	<reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
2919 	<reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
2920 	<reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
2921 	<reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
2922 	<reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
2923 	<reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
2924 	<reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
2925 	<reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
2926 	<reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
2927 	<reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
2928 	<reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
2929 	<reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
2930 	<reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
2931 	<reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
2932 	<reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
2934 	<reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/>
2935 	<reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit">
2936 		<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
2939 	<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/>
2940 	<reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit">
2944 	<array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit">
2945 		<reg32 offset="0x0" name="REG">
2949 				direction (0,0 is upper left, 0,1 is leftmost bin
2954 			<bitfield name="X" low="0" high="9" type="uint"/>
2970 	<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/>
2971 	<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/>
2972 	<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/>
2973 	<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/>
2974 	<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/>
2975 	<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/>
2977 	<array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit">
2985 		<reg32 offset="0x0" name="REG"/>
2988 …<array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_…
2993 		<reg32 offset="0x0" name="REG"/>
2996 …<array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_…
3001 		<reg32 offset="0x0" name="REG"/>
3004 	<reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/>
3006 	<reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/>
3007 	<reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/>
3008 	<!-- always 0x03200000 ? -->
3009 	<reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"  usage="cmd"/>
3013 		<bitfield name="X" low="0" high="13" type="uint"/>
3017 	<reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit">
3018 		<bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
3032 		<bitfield name="CLIP_MASK" low="0" high="7"/>
3035 	<reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
3036 	<reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
3037 	<reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/>
3038 	<reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/>
3040 	<reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit">
3042 		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
3052 	<reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit">
3053 		<bitfield name="HORZ" low="0" high="8" type="uint"/>
3058 	<reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/>
3060 	<reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/>
3062 	<reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/>
3063 	<reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/>
3064 	<reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/>
3065 	<reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/>
3067 	<!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> -->
3069 	<!-- 0x8006-0x800f invalid -->
3070 	<array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit">
3071 		<reg32 offset="0" name="XOFFSET" type="float"/>
3078 	<array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit">
3079 		<reg32 offset="0" name="MIN" type="float"/>
3083 	<reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit">
3084 		<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
3107 	<reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit">
3108 		<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
3111 …<reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="r…
3112 	<!-- 0x8093 invalid -->
3113 	<reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit">
3114 		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3116 	<reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/>
3117 	<reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/>
3118 	<reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/>
3120 	<reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit">
3121 		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3125 	<reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd">
3126 		<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
3131 	<reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL">
3132 		<bitfield name="UNK0" pos="0" type="boolean"/>
3137 		<bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
3140 	<reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
3141 	<reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
3142 	<reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/>
3143 	<!-- 0x809e/0x809f invalid -->
3146 		<value value="0x0" name="DIST_SCREEN_COORD"/>
3147 		<value value="0x1" name="DIST_ALL_TO_RB0"/>
3151 		<value value="0x0" name="NO_FLUSH"/>
3164 		<value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/>
3174 		<value value="0x3" name="FLUSH_PER_OVERLAP"/>
3179 		<value value="0x0" name="TYPE_TILED"/>
3180 		<value value="0x1" name="TYPE_WRITER"/>
3185 		<value value="0x0" name="LR_TB"/>
3186 		<value value="0x1" name="RL_TB"/>
3187 		<value value="0x2" name="LR_BT"/>
3188 		<value value="0x3" name="RB_BT"/>
3191 	<reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit">
3192 		<bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/>
3204 		<value value="0x0" name="RENDERING_PASS"/>
3205 		<value value="0x1" name="BINNING_PASS"/>
3209 		<value value="0" name="BUFFERS_IN_GMEM"/>
3214 		<value value="0x0" name="LRZ_FEEDBACK_NONE"/>
3215 		<value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/>
3216 		<value value="0x2" name="LRZ_FEEDBACK_EARLY_LRZ_LATE_Z"/>
3218 		<value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z"/>
3219 		<value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/>
3222 	<reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit">
3223 		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3238 	<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit">
3239 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3243 	<reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit">
3244 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3249 		<bitfield name="UNK0" pos="0"/>
3254 		<bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
3264 	<reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
3265 	<reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
3266 	<reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
3268 	<reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/>
3270 	<!-- 0x80a7-0x80ae invalid -->
3271 	<reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/>
3274 		<bitfield name="X" low="0" high="15" type="uint"/>
3277 	<array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit">
3278 		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
3281 	<array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit">
3282 		<reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
3286 	<reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
3287 	<reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
3289 	<!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate -->
3290 	<reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/>
3291 	<reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/>
3292 	<reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/>
3293 	<reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/>
3294 	<reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/>
3295 	<reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/>
3298 		<value value="0x1" name="LRZ_DIR_LE"/>
3299 		<value value="0x2" name="LRZ_DIR_GE"/>
3300 		<value value="0x3" name="LRZ_DIR_INVALID"/>
3303 	<reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit">
3304 		<bitfield name="ENABLE" pos="0" type="boolean"/>
3321 			buffer, in case of mismatched direction writes 0 (disables LRZ).
3333 		<value value="0" name="FRAGCOORD_CENTER"/>
3337 	<reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit">
3338 		<bitfield name="SAMPLEID" pos="0" type="boolean"/>
3342 	<reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit">
3343 		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3345 	<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/>
3346 	<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit">
3348 		<bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
3355 	to store 1b/block.  It appears that '0' means block has original
3382 …<reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp…
3383 	<!-- 0x8108 invalid -->
3384 	<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit">
3385 		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
3395 	<reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd">
3396 		<bitfield name="BASE_LAYER" low="0" high="10" type="uint"/>
3401 	<reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit">
3402 		<bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/>
3406 	<!-- 0x810c-0x810f invalid -->
3408 	<reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/>
3411 	<reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/>
3413 	<reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3414 		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3419 	<reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
3420 	<reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
3422 	<!-- 0x8112-0x83ff invalid -->
3425 		<value value="0x0" name="ROTATE_0"/>
3426 		<value value="0x1" name="ROTATE_90"/>
3427 		<value value="0x2" name="ROTATE_180"/>
3428 		<value value="0x3" name="ROTATE_270"/>
3429 		<value value="0x4" name="ROTATE_HFLIP"/>
3430 		<value value="0x5" name="ROTATE_VFLIP"/>
3434 		<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
3450 	<reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
3455 	<reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/>
3456 	<reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/>
3457 	<reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/>
3458 	<reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/>
3459 	<reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/>
3460 	<reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/>
3461 	<reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
3462 	<reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
3463 	<reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
3464 	<reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/>
3465 	<reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/>
3466 	<!-- 0x840c-0x85ff invalid -->
3468 	<!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
3469 	<reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd">
3473 	<reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
3474 	<reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/>
3475 	<array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/>
3476 	<array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/>
3477 	<array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/>
3479 	<!-- note 0x8620-0x87ff are not all invalid
3480 	(in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
3484 	<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit">
3485 		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3493 	<reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit">
3494 		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3501 	<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit">
3516 	<reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3525 	<reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit">
3529 	<reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit">
3530 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3534 	<reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit">
3535 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
3539 	<reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
3540 	<reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/>
3541 	<reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/>
3542 	<!-- 0x8807-0x8808 invalid -->
3547 	<reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit">
3549 		<bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
3558 	<reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit">
3560 		<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
3570 	<reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit">
3571 		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
3576 	<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit">
3577 		<bitfield name="MRT" low="0" high="3" type="uint"/>
3579 	<reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit">
3580 		<bitfield name="RT0" low="0" high="3"/>
3589 	<reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd">
3590 		<bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
3599 	<reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit">
3601 		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
3611 	<reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit">
3612 		<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
3614 	<reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/>
3615 	<reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/>
3616 	<!-- 0x8813-0x8817 invalid -->
3617 	<!-- always 0x0 ? -->
3618 	<reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/>
3619 	<!-- 0x8819-0x881e all 32 bits -->
3620 	<reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/>
3621 	<reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/>
3622 	<reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/>
3623 	<reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/>
3624 	<reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/>
3625 	<reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/>
3626 	<!-- 0x881f invalid -->
3627 	<array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit">
3628 		<reg32 offset="0x0" name="CONTROL">
3629 			<bitfield name="BLEND" pos="0" type="boolean"/>
3635 		<reg32 offset="0x1" name="BLEND_CONTROL">
3636 			<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
3643 		<reg32 offset="0x2" name="BUF_INFO" variants="A6XX">
3644 			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3649 		<reg32 offset="0x2" name="BUF_INFO" variants="A7XX-">
3650 			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3661 		<reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
3662 		<reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
3670 		<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
3672 		<reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
3675 	<reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/>
3676 	<reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/>
3677 	<reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/>
3678 	<reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/>
3679 	<reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd">
3680 		<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
3684 	<reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit">
3686 		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
3693 	<!-- 0x8866-0x886f invalid -->
3694 	<reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit">
3695 		<bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
3698 	<reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit">
3699 		<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
3710 	<reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit">
3711 		<bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/>
3714 	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit">
3715 		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3719 	<reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit">
3720 		<bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
3726 …<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="r…
3727 …<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" us…
3728 	<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
3729 …<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit…
3731 	<reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/>
3732 	<reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/>
3733 	<!-- 0x887a-0x887f invalid -->
3734 	<reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit">
3735 		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
3753 	<reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit">
3754 		<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
3756 	<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit">
3757 		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
3760 	<reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit">
3761 		<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
3765 …<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage=…
3766 …<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" …
3767 	<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/>
3768 …<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_bl…
3769 	<reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit">
3770 		<bitfield name="REF" low="0" high="7"/>
3773 	<reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit">
3774 		<bitfield name="MASK" low="0" high="7"/>
3777 	<reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit">
3778 		<bitfield name="WRMASK" low="0" high="7"/>
3781 	<!-- 0x888a-0x888f invalid -->
3782 	<reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
3783 	<reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd">
3784 		<bitfield name="DISABLE" pos="0" type="boolean"/>
3787 	<!-- 0x8892-0x8897 invalid -->
3788 	<reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit">
3789 		<bitfield name="ENABLE" pos="0" type="boolean"/>
3791 	<reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/>
3792 	<!-- 0x8899-0x88bf invalid -->
3794 	<reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/>
3795 	<reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/>
3796 	<!-- 0x88c2-0x88cf invalid-->
3797 	<reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit">
3798 		<bitfield name="UNK0" low="0" high="12"/>
3801 	<reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/>
3802 	<reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/>
3804 	<reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit">
3805 		<bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
3808 	<reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/>
3809 	<reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit">
3812 	<reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/>
3814 	<reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit">
3815 		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3823 	<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/>
3824 …<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_bl…
3826 …<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage=…
3827 	<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/>
3828 	<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit">
3829 		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3833 	<reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/>
3834 	<reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/>
3835 	<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>
3836 	<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>
3839 	<reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">
3840 …<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color rest…
3842 		<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
3850 				then probably a component mask, I always see 0xf
3856 …a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separ…
3857 			a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
3863 	<reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit">
3865 		<bitfield name="UNK0" pos="0" type="boolean"/>
3869 		<value value="0x0" name="CCU_CACHE_SIZE_FULL"/>
3870 		<value value="0x1" name="CCU_CACHE_SIZE_HALF"/>
3871 		<value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/>
3872 		<value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/>
3874 	<reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd">
3875 		<bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/>
3889 	<!-- 0x88e6-0x88ef invalid -->
3890 	<!-- always 0x0 ? -->
3891 	<reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/>
3893 	<reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
3894 	<reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
3895 		<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3898 	<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
3900 	<reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/>
3901 	<!-- 0x88f6-0x88ff invalid -->
3902 …<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"…
3903 	<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit">
3904 		<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
3909 	<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit">
3910 		<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
3912 			<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
3916 	<!-- 0x891b-0x8926 invalid -->
3921 	<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/>
3922 	<!-- 0x8929-0x89ff invalid -->
3924 	<!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
3930 	<reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/>
3931 	<reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/>
3932 	<reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/>
3933 	<reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/>
3935 	<reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/>
3936 	<reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/>
3939 		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3958 		<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
3967 	<!-- 0x8c02-0x8c16 invalid -->
3968 	<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_dst_surf_info" usage="rp_blit"/>
3969 	<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/>
3970 …<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit…
3972 	<reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/>
3973 …<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="r…
3974 	<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/>
3976 	<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/>
3977 …<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp…
3979 	<reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/>
3980 …<reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usa…
3982 	<!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers -->
3984 	<reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/>
3985 	<reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/>
3986 	<reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/>
3987 	<reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/>
3989 	<reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/>
3991 	<!-- 0x8c35-0x8dff invalid -->
3993 	<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
3994 	<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
3995 	<!-- 0x8e00-0x8e03 invalid -->
3996 	<reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
3997 	<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
3998 	<!-- 0x02080000 in GMEM, zero otherwise?  -->
3999 	<reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/>
4001 	<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX">
4002 		<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
4018 		<!--TODO: valid mask 0xfffffc1f -->
4020 	<reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-">
4021 		<bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/>
4025 	<reg32 offset="0x8e08" name="RB_NC_MODE_CNTL">
4026 		<bitfield name="MODE" pos="0" type="boolean"/>
4034 	<reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/>
4035 	<!-- 0x8e09-0x8e0f invalid -->
4036 	<array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/>
4037 	<array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/>
4038 	<!-- 0x8e1d-0x8e1f invalid -->
4039 	<!-- 0x8e20-0x8e25 more perfcntr sel? -->
4040 	<!-- 0x8e26-0x8e27 invalid -->
4041 	<reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/>
4042 	<!-- 0x8e29-0x8e2b invalid -->
4043 	<array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/>
4044 	<array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/>
4045 	<reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/>
4046 	<reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
4047 	<!-- 0x8e3e-0x8e4f invalid -->
4049 	<reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/>
4051 	<reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/>
4052 	<!-- 0x8e53-0x8e7f invalid -->
4053 	<reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/>
4054 	<!-- 0x8e80-0x8e83 are valid -->
4055 	<!-- 0x8e84-0x90ff invalid -->
4057 	<!-- 0x9000-0x90ff invalid -->
4059 	<reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit">
4060 		<bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/>
4064 		<bitfield name="CLIP_MASK" low="0" high="7" type="uint"/>
4072 	<reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4073 	<reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4074 	<reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4076 	<reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4077 	<reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4078 	<reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/>
4081 		<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
4086 	<reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4087 	<reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4088 	<reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4090 	<reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4091 	<reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4092 	<reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/>
4094 	<reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit">
4096 		<bitfield name="RASTER_DISCARD" pos="0" type="boolean"/>
4099 	<reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit">
4100 		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4104 		<bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
4121 		<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
4129 		<bitfield name="ENABLE" pos="0" type="boolean"/>
4142 …<reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" u…
4143 …<reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" u…
4144 …<reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usa…
4145 …<reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage…
4148 		<value value="0" name="INTERP_SMOOTH"/>
4155 		<value value="0" name="PS_REPL_NONE"/>
4161 	<!-- 0x9109-0x91ff invalid -->
4162 	<array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit">
4164 		<reg32 offset="0x0" name="MODE"/>
4166 	<array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit">
4168 		<reg32 offset="0x0" name="MODE"/>
4171 	<!-- always 0x0 -->
4172 	<reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/>
4173 	<reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/>
4175 	<array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit">
4177 		<reg32 offset="0" name="DISABLE"/>
4180 	<reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit">
4184 			HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a
4187 			location 0, stream 0
4188 			location 2, stream 0
4190 			location 126, stream 0
4191 			location 0, stream 1
4195 			location 0, stream 2
4204 		<bitfield name="ADDR" low="0" high="7" type="hex"/>
4209 	<reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit">
4210 		<bitfield name="A_BUF" low="0" high="1" type="uint"/>
4218 	<reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/>
4220 	<array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd">
4221 		<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
4223 		<reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/>
4228 	<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd">
4229 		<bitfield name="INVERT" pos="0" type="boolean"/>
4231 	<!-- 0x9237-0x92ff invalid -->
4232 	<!-- always 0x0 ? -->
4233 	<reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/>
4241 		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4248 				output is enabled, otherwise 0.
4252 	<reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
4253 	<reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
4254 	<reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/>
4256 	<reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit">
4257 		<bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
4275 	<reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit">
4277 		It's offset by 1, and 0 means "disabled"
4279 		<bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/>
4285 	<reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit">
4286 		<bitfield name="DISABLE" pos="0" type="boolean"/>
4288 	<reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit">
4289 		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4291 	<reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4292 		<bitfield name="SIZE_GMEM" low="0" high="31"/>
4294 	<reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit">
4295 		<bitfield name="BASE_GMEM" low="0" high="31"/>
4297 	<reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit">
4298 		<bitfield name="SIZE_GMEM" low="0" high="31"/>
4301 	<!-- 0x9307-0x95ff invalid -->
4303 	<!-- TODO: 0x9600-0x97ff range -->
4304 …<reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff va…
4305 	<reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/>
4306 	<reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? -->
4307 	<reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/>
4308 	<array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/>
4309 	<array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/>
4310 	<!-- 0x960a-0x9623 invalid -->
4311 	<!-- TODO: regs from 0x9624-0x963a -->
4312 	<!-- 0x963b-0x97ff invalid -->
4314 	<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/>
4316 	<!-- always 0x0 ? -->
4317 	<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit">
4318 		<bitfield name="SIZE" low="0" high="10" type="uint"/>
4322 	<reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit">
4323 		<bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
4327 	<reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/>
4328 	<reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/>
4330 	<reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
4332 	<reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit">
4333 		<bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/>
4337 	<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit">
4341 	<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">
4342 		<bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/>
4344 	<!-- 0x980b-0x983f invalid -->
4346 	<!-- 0x9840 - 0x9842 are not readable -->
4347 	<reg32 offset="0x9840" name="PC_DRAW_CMD">
4348 		<bitfield name="STATE_ID" low="0" high="7"/>
4351 	<reg32 offset="0x9841" name="PC_DISPATCH_CMD">
4352 		<bitfield name="STATE_ID" low="0" high="7"/>
4355 	<reg32 offset="0x9842" name="PC_EVENT_CMD">
4358 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4362 		0x9880 written in a lot of places by SQE, same value gets written
4363 		to control reg 0x12a.  Set by CP_SET_MARKER, so lets name it after
4366 	<reg32 offset="0x9880" name="PC_MARKER"/>
4368 	<!-- 0x9843-0x997f invalid -->
4370 	<reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit">
4371 		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4373 	<reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit">
4374 		<bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/>
4377 	<reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit">
4379 		<bitfield name="STREAM" low="0" high="1" type="uint"/>
4384 	<reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit">
4386 		<bitfield name="STREAM" low="0" high="1" type="uint"/>
4390 	<reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit">
4392 		<bitfield name="STREAM" low="0" high="1" type="uint"/>
4400 	<reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/>
4401 	<!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of
4404 	<reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/>
4406 	<!-- 0x9982-0x9aff invalid -->
4408 	<reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/>
4416 		<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
4426 	<reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
4427 	<reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
4429 	<reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
4430 	<reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/>
4432 	<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/>
4434 	<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit">
4438 		<bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/>
4441 	<reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
4443 	<reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/>
4444 	<!-- 0x9b09-0x9bff invalid -->
4445 	<reg32 offset="0x9c00" name="PC_2D_EVENT_CMD">
4447 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
4450 	<!-- 0x9c01-0x9dff invalid -->
4451 	<!-- TODO: 0x9e00-0xa000 range incomplete -->
4452 	<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
4453 	<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
4454 	<reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/>
4455 	<reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/>
4456 	<reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/>
4457 …<reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage=…
4458 …<reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage…
4460 	<reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx">
4466 	<reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/>
4467 	<reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/>
4470 	<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
4471 		<bitfield name="UNK0" low="0" high="15"/>
4475 	<reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/>
4476 	<reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/>
4478 	<reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE">
4480 		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
4483 	<reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/>
4485 	<array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/>
4486 	<array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/>
4488 	<!-- always 0x0 -->
4489 	<reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/>
4491 	<reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit">
4492 		<bitfield name="FETCH_CNT" low="0" high="5" type="uint"/>
4495 	<reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit">
4496 		<bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
4502 	<reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit">
4503 		<bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid">
4515 	<reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit">
4516 		<bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/>
4521 	<reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit">
4522 		<bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/>
4524 	<reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit">
4525 		<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
4528 	<reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit">
4532 		<bitfield name="PRIMID4PSEN" pos="0" type="boolean"/>
4535 	<reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd">
4536 		<bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/>
4539 	<reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/>
4540 	<reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd">
4542 		<bitfield name="VERTEX" pos="0" type="boolean"/>
4547 	<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/>
4548 	<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/>
4549 	<array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit">
4550 		<reg64 offset="0x0" name="BASE" type="address" align="1"/>
4551 		<reg32 offset="0x2" name="SIZE" type="uint"/>
4552 		<reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/>
4554 	<array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit">
4555 		<reg32 offset="0x0" name="INSTR">
4557 			<bitfield name="IDX" low="0" high="4" type="uint"/>
4565 		<reg32 offset="0x1" name="STEP_RATE" type="uint"/>
4567 	<array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit">
4568 		<reg32 offset="0x0" name="INSTR">
4569 			<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
4574 	<reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/>
4576 	<reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/>
4578 	<reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
4579 	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/>
4580 	<array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/>
4587 		<value value="0" name="THREAD64"/>
4593 		<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
4597 			- used (half): 0-15 68-179 (cnt=128, max=179)
4598 …- used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 12…
4602 			- used (merged): 0-191 (cnt=192, max=191)
4621 		<bitfield name="BINDLESS_TEX" pos="0" type="boolean"/>
4638 		<bitfield name="OUT" low="0" high="5" type="uint"/>
4643 	<reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
4668 	<reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/>
4670 	<reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
4671 	<array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit">
4672 		<reg32 offset="0x0" name="REG">
4673 			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4686 	<array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit">
4687 		<reg32 offset="0x0" name="REG">
4688 			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4696 		<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9">
4713 		<bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/>
4763 		<bitfield name="OFFSET" low="0" high="18" shr="11"/>
4766 	<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
4767 	<reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/>
4768 	<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
4769 	<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
4770 	<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
4771 	<reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4772 	<reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4773 	<reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4774 …<reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
4775 	<reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4777 	<reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
4787 	<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/>
4788 	<reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/>
4790 	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
4791 	<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
4792 	<reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/>
4793 	<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
4794 	<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
4795 	<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
4796 	<reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4797 	<reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4798 	<reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4799 …<reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
4800 	<reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4802 	<reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
4806 	<reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/>
4808 	<!-- TODO: exact same layout as 0xa802-0xa81a -->
4809 	<reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
4810 	<array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit">
4811 		<reg32 offset="0x0" name="REG">
4812 			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4818 	<array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit">
4819 		<reg32 offset="0x0" name="REG">
4820 			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4827 	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
4828 	<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
4829 	<reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/>
4830 	<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
4831 	<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
4832 	<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
4833 	<reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4834 	<reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4835 	<reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4836 …<reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
4837 	<reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4839 	<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
4843 	<reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit">
4857 	<reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/>
4859 	<!-- TODO: exact same layout as 0xa802-0xa81a -->
4860 	<reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/>
4861 	<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit">
4862 		<reg32 offset="0x0" name="REG">
4863 			<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
4870 	<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit">
4871 		<reg32 offset="0x0" name="REG">
4872 			<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
4879 	<!-- TODO: exact same layout as 0xa81b-0xa825 -->
4880 	<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
4881 	<reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/>
4882 	<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
4883 	<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
4884 	<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
4885 	<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
4886 	<reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
4887 	<reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
4888 …<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
4889 	<reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
4891 	<reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/>
4892 	<reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/>
4893 	<reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/>
4894 	<reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/>
4895 	<reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/>
4896 	<reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/>
4897 	<reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/>
4898 	<reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/>
4900 	<!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 -->
4902 	<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit">
4926 	<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/>
4927 	<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/>
4928 	<reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/>
4929 	<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/>
4930 	<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/>
4931 	<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/>
4933 	<reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit">
4935 		<bitfield name="ENABLE_BLEND" low="0" high="7"/>
4940 	<reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit">
4942 		<bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
4951 	<reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit">
4952 		<bitfield name="RT0" low="0" high="3"/>
4961 	<reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit">
4962 		<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
4967 	<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit">
4968 		<bitfield name="MRT" low="0" high="3" type="uint"/>
4971 	<array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit">
4973 		<reg32 offset="0x0" name="REG">
4974 			<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
4979 	<array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit">
4980 		<reg32 offset="0" name="REG">
4981 			<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
4988 	<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit">
4989 		<bitfield name="COUNT" low="0" high="2" type="uint"/>
5005 	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit">
5006 		<reg32 offset="0" name="CMD" variants="A6XX">
5007 			<bitfield name="SRC" low="0" high="6" type="uint"/>
5019 …<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit…
5020 		<reg32 offset="0" name="CMD" variants="A7XX-">
5021 			<bitfield name="SRC" low="0" high="6" type="uint"/>
5031 	<array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit">
5032 		<reg32 offset="0" name="CMD">
5033 			<bitfield name="SAMP_ID" low="0" high="15" type="uint"/>
5037 	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/>
5038 	<reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? -->
5039 …<reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
5041 	<!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS -->
5046 	<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd">
5057 	<reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd">
5058 		<bitfield name="SHARED_SIZE" low="0" high="4" type="uint">
5060 				If 0 - all 32k of shared storage is enabled, otherwise
5062 				The ldl/stl offset seems to be rewritten to 0 when it is beyond
5065 				always return 0)
5072 	<reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/>
5073 	<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/>
5074 	<reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/>
5075 	<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/>
5076 	<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/>
5077 	<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/>
5078 	<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/>
5079 	<reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/>
5080 	<reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/>
5081 …<reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offs…
5082 	<reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/>
5083 	<reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/>
5086 	<reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd">
5087 		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5093 	<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd">
5095 		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5105 	<reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd">
5107 		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5121 	<reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/>
5122 	<reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/>
5123 	<reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/>
5124 	<reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/>
5135 …<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd…
5136 		<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
5137 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5141 …<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cm…
5142 		<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5143 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5151 	<reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
5152 	<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/>
5155 	<reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/>
5157 	<reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd">
5158 		<bitfield name="ENABLED" pos="0" type="boolean"/>
5160 	<reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd">
5165 				alias.1.b32.0 r3.x, c8.x
5166 				alias.1.b32.0 r2.x, c4.x
5167 				alias.1.b32.0 r1.x, c4.x
5168 				alias.1.b32.0 r0.x, c0.x
5170 			the SP_PS_ALIASED_COMPONENTS would be 0x00001111
5173 		<bitfield name="RT0" low="0" high="3"/>
5183 	<reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/>
5189                 return 0 on out-of-bound textureFetch().
5192 		<value value="0x1" name="ISAMMODE_CL"/>
5193 		<value value="0x2" name="ISAMMODE_GL"/>
5196 	<reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit">
5205 		<bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/>
5210 	<reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/>
5211 	<reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/>
5213 	<reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/>
5214 	<reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/>
5216 …<array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_bli…
5217 		<reg64 offset="0" name="DESCRIPTOR" variants="A6XX">
5218 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5222 …<array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_bl…
5223 		<reg64 offset="0" name="DESCRIPTOR" variants="A7XX-">
5224 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5233 	<reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/>
5234 	<reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/>
5236 	<reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/>
5239 		<bitfield name="NORM" pos="0" type="boolean"/>
5251 …<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage=…
5252 …<reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage…
5254 	<reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/>
5255 	<reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
5256 	<reg32 offset="0xae02" name="SP_NC_MODE_CNTL">
5257 		<!-- TODO: valid bits 0x3c3f, see kernel -->
5259 	<reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/>
5260 	<reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd">
5264 	<reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/>
5265 	<reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/>
5266 	<reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/>
5267 	<reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/>
5269 	<reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd">
5273 		<bitfield name="VS" pos="0" type="boolean"/>
5280 	<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
5281 	<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
5282 	<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/>
5283 	<reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/>
5284 	<reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/>
5285 	<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
5290 		<bitfield name="SPTP" low="0" high="3"/>
5292 	<reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
5293 	<reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/>
5294 	<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
5295 	<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
5296 	<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
5297 	<reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
5304 …<reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cm…
5305 	<reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/>
5306 	<reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/>
5308 	<reg32 offset="0xb190" name="SP_UNKNOWN_B190"/>
5309 	<reg32 offset="0xb191" name="SP_UNKNOWN_B191"/>
5313 	<reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit">
5314 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5317 	<reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit">
5318 		<bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
5323 	<reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/>
5324 	<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/>
5325 …<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"…
5326 …<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"…
5327 	<reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/>
5328 	<reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd">
5329 		<bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/>
5332 	<reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/>
5339 …<reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A6XX" usage…
5340 	<reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit">
5341 		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
5344 …<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_bli…
5345 	<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit">
5346 		<bitfield name="UNK0" low="0" high="8"/>
5350 …<reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_src_surf_info" variants="A7XX-" usag…
5351 	<reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX">
5352 		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
5355 …<reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_bl…
5356 	<reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX">
5357 		<bitfield name="UNK0" low="0" high="8"/>
5362 	<reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/>
5363 …<reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" varia…
5364 	<reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/>
5366 	<reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/>
5367 …<reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" varia…
5368 	<reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/>
5370 …<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="…
5371 …<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" varian…
5373 …<reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage=…
5374 …<reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" varian…
5376 	<reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/>
5377 	<reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/>
5378 	<reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/>
5379 	<reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/>
5380 	<reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/>
5382 	<reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/>
5383 	<reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/>
5384 	<reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/>
5385 	<reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/>
5386 	<reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/>
5387 	<reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/>
5388 …<reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"…
5390 	<!-- always 0x100000 or 0x1000000? -->
5391 	<reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/>
5392 	<reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
5393 	<reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd">
5399 	<reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL">
5400 		<bitfield name="MODE" pos="0" type="boolean"/>
5406 …<reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage…
5408 	<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/>
5409 	<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/>
5410 	<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/>
5411 	<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/>
5412 	<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/>
5414 …<reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage…
5415 …<reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage…
5416 …<reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage…
5417 …<reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage…
5418 …<reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage…
5420 	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/>
5421 	<array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/>
5423 	<!-- TODO: 4 more perfcntr sel at 0xb620 ? -->
5426 		<bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
5431 …<reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit…
5432 …<reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit…
5433 …<reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit…
5434 …<reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit…
5436 …<reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5437 …<reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5438 …<reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5439 …<reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5441 	<reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit">
5443 		<bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/>
5446 	<!-- Always 0 -->
5447 	<reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/>
5450 	<reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/>
5452 	<reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit">
5453 		<bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/>
5460 	<reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/>
5461 	<reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/>
5462 	<reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/>
5467 		<bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/>
5473 		<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
5479 		<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
5485 		<bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/>
5489 …<reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_…
5490 …<reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- neve…
5491 	<reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit">
5495 		<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5497 	<reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit">
5498 		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5504 …<reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" us…
5505 …<reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" us…
5506 …<reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" us…
5507 	<reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/>
5508 …<reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp…
5509 	<reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit">
5510 			<bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/>
5512 	<reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit">
5513 		<bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
5519 …<reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" u…
5520 …<reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" u…
5521 …<reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" u…
5522 	<reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/>
5525 	<reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit">
5526 		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5532 	<reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit">
5533 		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5535 	<reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit">
5536 		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5538 	<reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit">
5539 		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5541 	<reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit">
5542 		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5544 	<reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit">
5545 		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5547 	<reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit">
5548 		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5550 	<reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit">
5555 		<bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
5560 	<reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit">
5562 		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5572 	<reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/>
5573 	<reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/>
5574 	<reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/>
5577 	<reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit">
5578 		<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
5584 	<reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit">
5585 		<bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
5587 	<reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit">
5588 		<bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
5590 	<reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit">
5591 		<bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
5593 	<reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit">
5594 		<bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
5596 	<reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit">
5597 		<bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
5599 	<reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit">
5600 		<bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
5603 	<reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/>
5604 	<reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/>
5605 	<reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/>
5614 	<reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit">
5616 		<bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/>
5625 	<reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd">
5632 	<reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/>
5633 	<reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/>
5634 	<reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/>
5637 …<array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="r…
5638 		<reg64 offset="0" name="DESCRIPTOR">
5639 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5645 	<reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd">
5646 		<bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/>
5652 	<reg32 offset="0xbb00" name="HLSQ_DRAW_CMD" variants="A6XX">
5653 		<bitfield name="STATE_ID" low="0" high="7"/>
5656 	<reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD" variants="A6XX">
5657 		<bitfield name="STATE_ID" low="0" high="7"/>
5660 	<reg32 offset="0xbb02" name="HLSQ_EVENT_CMD" variants="A6XX">
5663 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5666 	<reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd">
5674 		<bitfield name="VS_STATE" pos="0" type="boolean"/>
5693 	<reg32 offset="0xab1c" name="HLSQ_DRAW_CMD" variants="A7XX-">
5694 		<bitfield name="STATE_ID" low="0" high="7"/>
5697 	<reg32 offset="0xab1d" name="HLSQ_DISPATCH_CMD" variants="A7XX-">
5698 		<bitfield name="STATE_ID" low="0" high="7"/>
5701 	<reg32 offset="0xab1e" name="HLSQ_EVENT_CMD" variants="A7XX-">
5703 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5706 	<reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd">
5714 		<bitfield name="VS_STATE" pos="0" type="boolean"/>
5729 …<reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit…
5730 …<reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_bli…
5732 	<array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/>
5734 	<reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd">
5753 		<bitfield name="ENABLE" pos="0" type="boolean"/>
5757 	<array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd">
5758 		<reg64 offset="0" name="DESCRIPTOR">
5759 			<bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/>
5764 	<reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD">
5766 		<bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/>
5769 …<reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid …
5770 	<reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/>
5771 	<reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/>
5772 	<reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
5773 	<reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/>
5774 	<array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/>
5776 	<!-- TODO: some valid registers between 0xbe20 and 0xbe33 -->
5777 	<reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
5779 	<reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/>
5781 	<!-- Don't know if these are SP, always 0 -->
5782 	<reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/>
5783 	<reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/>
5784 	<reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/>
5798 	<reg32 offset="0xd600" name="CP_EVENT_START">
5799 		<bitfield name="STATE_ID" low="0" high="7"/>
5801 	<reg32 offset="0xd601" name="CP_EVENT_END">
5802 		<bitfield name="STATE_ID" low="0" high="7"/>
5804 	<reg32 offset="0xd700" name="CP_2D_EVENT_START">
5805 		<bitfield name="STATE_ID" low="0" high="7"/>
5807 	<reg32 offset="0xd701" name="CP_2D_EVENT_END">
5808 		<bitfield name="STATE_ID" low="0" high="7"/>
5816 		<value name="A6XX_TEX_NEAREST" value="0"/>
5822 		<value name="A6XX_TEX_REPEAT" value="0"/>
5829 		<value name="A6XX_TEX_ANISO_1" value="0"/>
5836 		<value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/>
5841 	<reg32 offset="0" name="0">
5842 		<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
5852 		<bitfield name="CLAMPENABLE" pos="0" type="boolean">
5854 				clamp result to [0, 1] if the format is unorm or
5867 		<bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/>
5877 		<value name="A6XX_TEX_X" value="0"/>
5885 		<value name="A6XX_TEX_1D" value="0"/>
5891 	<reg32 offset="0" name="0">
5892 		<bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
5912 		<bitfield name="WIDTH" low="0" high="14" type="uint"/>
5926 		<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
5938 		<bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/>
5956 		<bitfield name="BASE_HI" low="0" high="16"/>
5961 		<bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/>
5970 		<bitfield name="FLAG_HI" low="0" high="16"/>
5974 		<bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
5977 		<bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
5990 	<reg32 offset="0" name="0">
5991 		<bitfield name="BASE_LO" low="0" high="31"/>
5994 		<bitfield name="BASE_HI" low="0" high="16"/>
6000 	<reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
6001 	<reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
6002 	<reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
6003 	<reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
6004 	<reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
6005 	<reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
6006 	<reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
6007 	<reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
6008 	<reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
6009 	<reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
6010 	<reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
6011 	<reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
6012 	<reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
6013 	<reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
6014 	<reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
6015 	<reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
6016 	<reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
6017 	<reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
6018 	<reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
6019 	<reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
6020 	<reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
6021 	<reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
6022 	<reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
6023 	<reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
6024 	<reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
6025 	<reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
6029 	<reg32 offset="0x0" name="MEM_0"/>
6033 	<reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
6034 		<bitfield high="7" low="0" name="PING_INDEX"/>
6037 	<reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
6038 	<reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
6039 	<reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
6040 	<reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
6041 		<bitfield high="5" low="0" name="TRACEEN"/>
6045 	<reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
6048 	<reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
6049 	<reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
6050 	<reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
6051 	<reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
6052 	<reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
6053 	<reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
6054 	<reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
6055 	<reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
6056 	<reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
6057 		<bitfield high="3" low="0" name="BYTEL0"/>
6066 	<reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
6067 		<bitfield high="3" low="0" name="BYTEL8"/>
6077 	<reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
6078 	<reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
6082 	<reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
6083 	<reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
6084 	<reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/>
6085 	<reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-">
6086 		<bitfield pos="0" name="FASTBLEND" type="boolean"/>