Lines Matching +full:blit +full:- +full:engine
1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
32 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/> <!-- GL_RGB10_A2 -->
33 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/> <!-- GL_RGB10_A2UI -->
34 <value value="0x42" name="RB5_R11G11B10_FLOAT"/> <!-- GL_R11F_G11F_B10F -->
251 <value value="8" name="BLIT_ZS"/> <!-- depth or combined depth+stencil -->
252 <value value="9" name="BLIT_S"/> <!-- separate stencil -->
255 <!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
851 <!-- CP Interrupt bits -->
861 <!-- CP registers -->
943 <!-- RBBM registers -->
948 <!--
953 -->
1415 <!-- VSC registers -->
1419 <!-- b17 maybe BYPASS like RB_CNTL, but reg not written for bypass -->
1423 <reg32 offset="0x0bc5" name="UNKNOWN_0BC5"/> <!-- always 00000000? -->
1424 <reg32 offset="0x0bc6" name="UNKNOWN_0BC6"/> <!-- always 00000000? -->
1451 <!-- used for some blits?? -->
1454 <!-- GRAS registers -->
1469 <reg32 offset="0x0cc4" name="RB_DBG_ECO_CNTL"/> <!-- always 00100000? -->
1471 <reg32 offset="0x0cc6" name="RB_MODE_CNTL"/> <!-- always 00000044? -->
1472 <reg32 offset="0x0cc7" name="RB_CCU_CNTL"/> <!-- always b0056080 or 10000000? -->
1500 <reg32 offset="0x0d02" name="PC_MODE_CNTL"/> <!-- always 0000001f? -->
1520 <reg32 offset="0x0e06" name="HLSQ_MODE_CNTL"/> <!-- always 00000001? -->
1534 <reg32 offset="0x0e42" name="VFD_MODE_CNTL"/> <!-- always 00000000? -->
1591 <reg32 offset="0x0ec2" name="SP_MODE_CNTL"/> <!-- always 0000001e? -->
1610 <reg32 offset="0x0f02" name="TPL1_MODE_CNTL"/> <!-- always 00000544? -->
1626 <!--
1629 -->
1637 <!--
1640 -->
1643 <!--
1646 -->
1649 <!--
1652 -->
1655 <!--
1658 -->
1693 <!--
1701 -->
1824 <reg32 offset="0xe004" name="UNKNOWN_E004"/> <!-- always 00000000? -->
1826 <!-- see also RB_RENDER_CONTROL0 -->
1852 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1867 <!-- duplicates RB_DEPTH_INFO0: -->
1871 <reg32 offset="0xe099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL"/> <!-- always 00000000? -->
1872 <!--
1875 -->
1880 <!-- note, 0x4 for binning pass when frag writes z?? -->
1881 <reg32 offset="0xe0a1" name="GRAS_SC_BIN_CNTL"/> <!-- always 00000000? -->
1889 <reg32 offset="0xe0a4" name="GRAS_SC_SCREEN_SCISSOR_CNTL"/> <!-- always 00000000? -->
1899 ----
1903 a depth-prepass, used during the GMEM draws to discard primitives that
1921 <!--
1924 -->
1928 <!--
1930 -->
1945 <!--
1949 see mrt-fbo-* zs=2)
1950 -->
1954 <!-- why everything twice?? maybe read vs write? -->
1955 <!-- UBWC flag buffer enabled for depth/stencil: -->
1958 <!-- bitmask of MRTs using UBWC flag buffer: -->
1969 <!--
1972 -->
1974 <!-- see also GRAS_CNTL -->
1989 <!-- bit0 set except for binning pass.. -->
2020 <!--
2025 -->
2032 <!--
2035 -->
2071 <!-- per-mrt enable bit -->
2075 <!-- a guess? -->
2103 <!--
2108 -->
2135 ------
2137 Blits are triggered by CP_EVENT_WRITE:BLIT, compared to previous
2141 For gmem->mem blob uses RB_BLIT_CNTL.BUF to specify src of
2142 blit (ie MRTn, ZS, etc) and RB_BLIT_DST_LO/HI for destination
2145 For mem->gmem blob uses just MRT0 or ZS and RB_BLIT_DST_LO/HI
2155 <!-- if b0 set, output is in TILE5_3 format -->
2157 <!--
2159 0x0 mem->gmem
2160 0xf gmem->mem with flag buffer (color)
2161 0x4 gmem->mem without flag buffer (color)
2163 also for gmem->mem preserving tiling
2164 -->
2169 <!-- array-pitch is size of layer -->
2180 1 - depth
2181 2 - stencil
2182 3 - depth+stencil
2191 -------------------------------
2203 …https://android.googlesource.com/platform/hardware/qcom/display/+/android-6.0.1_r40/msm8994/libgra…
2212 0 c073a000 c0732000 - level 0 flags is address
2225 so 0xc08c3000 - 0xc0732000 = 0x00191000 (1642496); each level
2232 { ARRAY_PITCH = 1642496 | 0x18800000 } - NOTE c2dc always has 0x18800000 but
2246 <!-- array-pitch is size of layer -->
2252 <!-- array-pitch is size of layer -->
2261 plus # of transform-feedback (streamout) varyings if using the
2276 <!-- one bit per varying component: -->
2282 <!-- there can be up to 8 total clip/cull distance outputs,
2285 -->
2292 <!--
2294 be the max-OUTLOC position, but it is only set when VS writes psize
2296 -->
2302 Stream-Out:
2303 -----------
2311 components of stream-out output. Order matches up to OUTLOC,
2348 <!-- always 0x10000 when SO enabled.. -->
2363 <reg32 offset="3" name="NCOMP"/> <!-- component count -->
2370 <!-- # of varyings plus four for gl_Position (plus one if gl_PointSize) -->
2373 …ield name="COUNT_PRIMITIVES" pos="9" type="boolean"/><!-- enabled when gl_PrimitiveIDIn is used -->
2390 <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- vertices - 1 -->
2391 <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- invoc - 1 -->
2411 …e="REGID_PATCHID" low="0" high="7" type="a3xx_regid"/><!-- same as VFD_CONTROL_3.REGID_PATCHID? -->
2421 <!-- b0 set if gl_PrimitiveID used in fs ?? -->
2433 <!-- IDX appears to index into VFD_FETCH[] -->
2441 <reg32 offset="0x1" name="STEP_RATE"/> <!-- ??? -->
2451 <!-- 0x0 for compute, 0x10 for 3d? -->
2461 <!--
2462 no idea high bit.. could be this is amount of on-chip memory used
2464 -->
2468 <!-- bit1 almost always set -->
2469 <!-- set for "buffer mode" (ie. shader small enough to fit internally) -->
2471 <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2477 <!-- seems to be nesting level for flow control:.. -->
2480 <!-- assuming things appear in same relative order as a4xx: -->
2481 <!-- duplicated exactly w/ corresponding HLSQ_ regs starting at 0xe78b.. -->
2492 <!-- # of VS outputs including pos/psize -->
2503 <!--
2509 -->
2547 <!-- per-mrt enable bit -->
2572 <!--
2576 -->
2586 <!-- e5f9 something compute related.. seems to change when HLSQ_CS_CNTL_1 changes -->
2617 <!-- either blob is doing it wrong, or this is not per-stage anymore: -->
2621 <!--
2625 -->
2664 <!-- 24 or more (full size) GPRS and blob uses TWO_QUADS instead of FOUR_QUADS -->
2669 <!-- I guess.. not set exactly same as a4xx, but similar: -->
2674 <!-- SAMPLEID is loaded into a half-precision register: -->
2680 <!-- register loaded with position (bary.f) -->
2692 <!--
2696 -->
2715 <!-- localsize is value minus one: -->
2740 <!-- possibly one of these is KERNELDIMCONSTID? -->
2741 <!--
2747 -->
2772 <!--
2773 Separate blit/2d or dma engine? Seems to get used sometimes for
2775 in render-mode 0x5..
2778 to use the CP_EVENT_WRITE:BLIT style of doing things. See
2779 cubemap-0003 (40x40) vs cubemap-0004 (256x256).
2781 see cube-0000, cubemap-(1..3 but not 4+), quad-textured-10..17
2784 blit coords are in CP packet. Play more w/ glTexSubImage2D()
2790 regs 0x2000 to 0x2004 (plus all-zero regs 0x2005-0x2009) look
2795 -->
2796 <reg32 offset="0x2100" name="RB_2D_BLIT_CNTL"/> <!-- same as 0x2180 -->
2806 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2832 <reg32 offset="0x2180" name="GRAS_2D_BLIT_CNTL"/> <!-- same as 0x2100 -->
2833 <!-- looks same as 0x2107: -->
2835 <!-- looks same as 0x2110: -->
2837 <!--
2841 0x2184 0x9 for copy, 0x1 for blit (maybe bitmask of enabled src/dst???)
2842 -->
2848 <enum name="a5xx_tex_filter"> <!-- same as a4xx? -->
2853 <enum name="a5xx_tex_clamp"> <!-- same as a4xx? -->
2860 <enum name="a5xx_tex_aniso"> <!-- same as a4xx? -->
2875 … name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
2886 <!--
2887 offset into border-color buffer? Blob always uses 0x80 for FS state
2888 if both VS and FS have border-color.
2891 different border-color states per texture.. Looks something like:
2900 -->
2908 <enum name="a5xx_tex_swiz"> <!-- same as a4xx? -->
2916 <enum name="a5xx_tex_type"> <!-- same as a4xx? -->
2940 <!--
2945 …behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.bu…
2946 -->
2948 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) -->
2955 <!--
2960 -->
2963 <!--
2967 -->
2986 <!--
2990 -->
2996 <!-- no BASE_HI here? Maybe this is only used for 32b mode? -->
3004 <!-- bytes per pixel: -->
3035 <!-- size probably in high bits -->