Lines Matching +full:sm8550 +full:- +full:dpu
2 * SPDX-License-Identifier: GPL-2.0
58 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
63 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
65 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
67 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
68 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
71 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
73 msm_mdss->reg_bus_path = reg_bus_path; in msm_mdss_parse_data_bus_icc_path()
86 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); in msm_mdss_irq()
89 irq_hw_number_t hwirq = fls(interrupts) - 1; in msm_mdss_irq()
92 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, in msm_mdss_irq()
95 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", in msm_mdss_irq()
112 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); in msm_mdss_irq_mask()
123 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); in msm_mdss_irq_unmask()
139 struct msm_mdss *msm_mdss = domain->host_data; in msm_mdss_irqdomain_map()
157 dev = msm_mdss->dev; in _msm_mdss_irq_domain_add()
159 domain = irq_domain_add_linear(dev->of_node, 32, in _msm_mdss_irq_domain_add()
163 return -EINVAL; in _msm_mdss_irq_domain_add()
166 msm_mdss->irq_controller.enabled_mask = 0; in _msm_mdss_irq_domain_add()
167 msm_mdss->irq_controller.domain = domain; in _msm_mdss_irq_domain_add()
174 const struct msm_mdss_data *data = msm_mdss->mdss_data; in msm_mdss_setup_ubwc_dec_20()
176 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); in msm_mdss_setup_ubwc_dec_20()
181 const struct msm_mdss_data *data = msm_mdss->mdss_data; in msm_mdss_setup_ubwc_dec_30()
182 u32 value = (data->ubwc_swizzle & 0x1) | in msm_mdss_setup_ubwc_dec_30()
183 (data->highest_bank_bit & 0x3) << 4 | in msm_mdss_setup_ubwc_dec_30()
184 (data->macrotile_mode & 0x1) << 12; in msm_mdss_setup_ubwc_dec_30()
186 if (data->ubwc_enc_version == UBWC_3_0) in msm_mdss_setup_ubwc_dec_30()
189 if (data->ubwc_enc_version == UBWC_1_0) in msm_mdss_setup_ubwc_dec_30()
192 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); in msm_mdss_setup_ubwc_dec_30()
197 const struct msm_mdss_data *data = msm_mdss->mdss_data; in msm_mdss_setup_ubwc_dec_40()
198 u32 value = (data->ubwc_swizzle & 0x7) | in msm_mdss_setup_ubwc_dec_40()
199 (data->ubwc_static & 0x1) << 3 | in msm_mdss_setup_ubwc_dec_40()
200 (data->highest_bank_bit & 0x7) << 4 | in msm_mdss_setup_ubwc_dec_40()
201 (data->macrotile_mode & 0x1) << 12; in msm_mdss_setup_ubwc_dec_40()
203 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); in msm_mdss_setup_ubwc_dec_40()
205 if (data->ubwc_enc_version == UBWC_3_0) { in msm_mdss_setup_ubwc_dec_40()
206 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); in msm_mdss_setup_ubwc_dec_40()
207 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); in msm_mdss_setup_ubwc_dec_40()
209 if (data->ubwc_dec_version == UBWC_4_3) in msm_mdss_setup_ubwc_dec_40()
210 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); in msm_mdss_setup_ubwc_dec_40()
212 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); in msm_mdss_setup_ubwc_dec_40()
213 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); in msm_mdss_setup_ubwc_dec_40()
234 data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL); in msm_mdss_generate_mdp5_mdss_data()
238 hw_rev = readl_relaxed(mdss->mmio + HW_REV); in msm_mdss_generate_mdp5_mdss_data()
247 data->ubwc_dec_version = UBWC_1_0; in msm_mdss_generate_mdp5_mdss_data()
248 data->ubwc_enc_version = UBWC_1_0; in msm_mdss_generate_mdp5_mdss_data()
253 data->highest_bank_bit = 2; in msm_mdss_generate_mdp5_mdss_data()
255 data->highest_bank_bit = 1; in msm_mdss_generate_mdp5_mdss_data()
265 return ERR_PTR(-EINVAL); in msm_mdss_get_mdss_data()
273 if (!mdss->mdss_data && mdss->is_mdp5) in msm_mdss_get_mdss_data()
274 mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss); in msm_mdss_get_mdss_data()
276 return mdss->mdss_data; in msm_mdss_get_mdss_data()
285 * the interconnect is enabled (non-zero bandwidth). Let's make sure in msm_mdss_enable()
288 for (i = 0; i < msm_mdss->num_mdp_paths; i++) in msm_mdss_enable()
289 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); in msm_mdss_enable()
291 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) in msm_mdss_enable()
292 icc_set_bw(msm_mdss->reg_bus_path, 0, in msm_mdss_enable()
293 msm_mdss->mdss_data->reg_bus_bw); in msm_mdss_enable()
295 icc_set_bw(msm_mdss->reg_bus_path, 0, in msm_mdss_enable()
298 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); in msm_mdss_enable()
300 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); in msm_mdss_enable()
308 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) in msm_mdss_enable()
318 switch (msm_mdss->mdss_data->ubwc_dec_version) { in msm_mdss_enable()
334 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", in msm_mdss_enable()
335 msm_mdss->mdss_data->ubwc_dec_version); in msm_mdss_enable()
336 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", in msm_mdss_enable()
337 readl_relaxed(msm_mdss->mmio + HW_REV)); in msm_mdss_enable()
338 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", in msm_mdss_enable()
339 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); in msm_mdss_enable()
350 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); in msm_mdss_disable()
352 for (i = 0; i < msm_mdss->num_mdp_paths; i++) in msm_mdss_disable()
353 icc_set_bw(msm_mdss->mdp_path[i], 0, 0); in msm_mdss_disable()
355 if (msm_mdss->reg_bus_path) in msm_mdss_disable()
356 icc_set_bw(msm_mdss->reg_bus_path, 0, 0); in msm_mdss_disable()
363 struct platform_device *pdev = to_platform_device(msm_mdss->dev); in msm_mdss_destroy()
366 pm_runtime_suspend(msm_mdss->dev); in msm_mdss_destroy()
367 pm_runtime_disable(msm_mdss->dev); in msm_mdss_destroy()
368 irq_domain_remove(msm_mdss->irq_controller.domain); in msm_mdss_destroy()
369 msm_mdss->irq_controller.domain = NULL; in msm_mdss_destroy()
411 return -EINVAL; in mdp5_mdss_parse_clock()
413 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); in mdp5_mdss_parse_clock()
415 return -ENOMEM; in mdp5_mdss_parse_clock()
421 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); in mdp5_mdss_parse_clock()
436 ret = msm_mdss_reset(&pdev->dev); in msm_mdss_init()
440 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); in msm_mdss_init()
442 return ERR_PTR(-ENOMEM); in msm_mdss_init()
444 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); in msm_mdss_init()
446 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); in msm_mdss_init()
447 if (IS_ERR(msm_mdss->mmio)) in msm_mdss_init()
448 return ERR_CAST(msm_mdss->mmio); in msm_mdss_init()
450 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); in msm_mdss_init()
452 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); in msm_mdss_init()
457 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); in msm_mdss_init()
459 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); in msm_mdss_init()
461 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); in msm_mdss_init()
464 msm_mdss->num_clocks = ret; in msm_mdss_init()
465 msm_mdss->is_mdp5 = is_mdp5; in msm_mdss_init()
467 msm_mdss->dev = &pdev->dev; in msm_mdss_init()
480 pm_runtime_enable(&pdev->dev); in msm_mdss_init()
528 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); in mdss_probe()
529 struct device *dev = &pdev->dev; in mdss_probe()
539 * MDP5/DPU based devices don't have a flat hierarchy. There is a top in mdss_probe()
540 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. in mdss_probe()
541 * Populate the children devices, find the MDP5/DPU node, and then add in mdss_probe()
544 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); in mdss_probe()
558 of_platform_depopulate(&pdev->dev); in mdss_remove()
711 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
712 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
713 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
714 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
715 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
716 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
717 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
718 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
719 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
720 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
721 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
722 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
723 { .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
724 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
725 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
726 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
727 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
728 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
729 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
730 { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
739 .name = "msm-mdss",