Lines Matching +full:sm6350 +full:- +full:mdss
2 * SPDX-License-Identifier: GPL-2.0
23 #include <generated/mdss.xml.h>
56 path0 = devm_of_icc_get(dev, "mdp0-mem");
60 msm_mdss->mdp_path[0] = path0;
61 msm_mdss->num_mdp_paths = 1;
63 path1 = devm_of_icc_get(dev, "mdp1-mem");
65 msm_mdss->mdp_path[1] = path1;
66 msm_mdss->num_mdp_paths++;
69 reg_bus_path = of_icc_get(dev, "cpu-cfg");
71 msm_mdss->reg_bus_path = reg_bus_path;
84 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);
87 irq_hw_number_t hwirq = fls(interrupts) - 1;
90 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
93 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
110 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
121 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
137 struct msm_mdss *msm_mdss = domain->host_data;
155 dev = msm_mdss->dev;
157 domain = irq_domain_create_linear(of_fwnode_handle(dev->of_node), 32,
161 return -EINVAL;
164 msm_mdss->irq_controller.enabled_mask = 0;
165 msm_mdss->irq_controller.domain = domain;
172 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
173 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
174 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
176 if (data->ubwc_bank_spread)
179 if (data->ubwc_enc_version == UBWC_1_0)
182 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
187 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
188 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
189 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
191 if (data->macrotile_mode)
194 if (data->ubwc_enc_version == UBWC_3_0)
197 if (data->ubwc_enc_version == UBWC_1_0)
200 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
205 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
206 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
207 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);
209 if (data->ubwc_bank_spread)
212 if (data->macrotile_mode)
215 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
217 if (data->ubwc_enc_version == UBWC_3_0) {
218 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
219 writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
221 if (data->ubwc_dec_version == UBWC_4_3)
222 writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
224 writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
225 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
231 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;
232 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
233 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
235 if (data->ubwc_bank_spread)
238 if (data->macrotile_mode)
241 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
243 writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
244 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
253 * the interconnect is enabled (non-zero bandwidth). Let's make sure
256 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
257 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
259 icc_set_bw(msm_mdss->reg_bus_path, 0,
260 msm_mdss->reg_bus_bw);
262 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
264 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
270 * mdss on mdp5 hardware. Skip it for now.
272 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
276 * ubwc config is part of the "mdss" region which is not accessible
282 switch (msm_mdss->mdss_data->ubwc_dec_version) {
301 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
302 msm_mdss->mdss_data->ubwc_dec_version);
303 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
304 readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));
305 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
306 readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));
317 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
319 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
320 icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
322 if (msm_mdss->reg_bus_path)
323 icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
330 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
333 pm_runtime_suspend(msm_mdss->dev);
334 pm_runtime_disable(msm_mdss->dev);
335 irq_domain_remove(msm_mdss->irq_controller.domain);
336 msm_mdss->irq_controller.domain = NULL;
351 "failed to acquire mdss reset\n");
368 * MDP5 MDSS uses at most three specified clocks.
378 return -EINVAL;
380 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
382 return -ENOMEM;
388 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
404 ret = msm_mdss_reset(&pdev->dev);
408 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
410 return ERR_PTR(-ENOMEM);
412 msm_mdss->mdss_data = qcom_ubwc_config_get_data();
413 if (IS_ERR(msm_mdss->mdss_data))
414 return ERR_CAST(msm_mdss->mdss_data);
416 mdss_data = of_device_get_match_data(&pdev->dev);
418 return ERR_PTR(-EINVAL);
420 msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;
422 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
423 if (IS_ERR(msm_mdss->mmio))
424 return ERR_CAST(msm_mdss->mmio);
426 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
428 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
433 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
435 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
437 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
440 msm_mdss->num_clocks = ret;
441 msm_mdss->is_mdp5 = is_mdp5;
443 msm_mdss->dev = &pdev->dev;
456 pm_runtime_enable(&pdev->dev);
463 struct msm_mdss *mdss = dev_get_drvdata(dev);
467 return msm_mdss_disable(mdss);
472 struct msm_mdss *mdss = dev_get_drvdata(dev);
476 return msm_mdss_enable(mdss);
503 struct msm_mdss *mdss;
504 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
505 struct device *dev = &pdev->dev;
508 mdss = msm_mdss_init(pdev, is_mdp5);
509 if (IS_ERR(mdss))
510 return PTR_ERR(mdss);
512 platform_set_drvdata(pdev, mdss);
516 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
520 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
523 msm_mdss_destroy(mdss);
532 struct msm_mdss *mdss = platform_get_drvdata(pdev);
534 of_platform_depopulate(&pdev->dev);
536 msm_mdss_destroy(mdss);
556 { .compatible = "qcom,mdss", .data = &data_153k6 },
557 { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
558 { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
559 { .compatible = "qcom,sa8775p-mdss", .data = &data_74k },
560 { .compatible = "qcom,sar2130p-mdss", .data = &data_74k },
561 { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
562 { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 },
563 { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 },
564 { .compatible = "qcom,sc7280-mdss", .data = &data_74k },
565 { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 },
566 { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 },
567 { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 },
568 { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 },
569 { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 },
570 { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 },
571 { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 },
572 { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 },
573 { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 },
574 { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 },
575 { .compatible = "qcom,sm8350-mdss", .data = &data_74k },
576 { .compatible = "qcom,sm8450-mdss", .data = &data_74k },
577 { .compatible = "qcom,sm8550-mdss", .data = &data_57k },
578 { .compatible = "qcom,sm8650-mdss", .data = &data_57k },
579 { .compatible = "qcom,sm8750-mdss", .data = &data_57k },
581 { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 },
590 .name = "msm-mdss",