Lines Matching +full:sm6115 +full:- +full:mdss
2 * SPDX-License-Identifier: GPL-2.0
22 #include <generated/mdss.xml.h>
26 #define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
52 path0 = devm_of_icc_get(dev, "mdp0-mem");
56 msm_mdss->mdp_path[0] = path0;
57 msm_mdss->num_mdp_paths = 1;
59 path1 = devm_of_icc_get(dev, "mdp1-mem");
61 msm_mdss->mdp_path[1] = path1;
62 msm_mdss->num_mdp_paths++;
65 reg_bus_path = of_icc_get(dev, "cpu-cfg");
67 msm_mdss->reg_bus_path = reg_bus_path;
80 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);
83 irq_hw_number_t hwirq = fls(interrupts) - 1;
86 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
89 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
106 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
117 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
133 struct msm_mdss *msm_mdss = domain->host_data;
151 dev = msm_mdss->dev;
153 domain = irq_domain_add_linear(dev->of_node, 32,
157 return -EINVAL;
160 msm_mdss->irq_controller.enabled_mask = 0;
161 msm_mdss->irq_controller.domain = domain;
168 const struct msm_mdss_data *data = msm_mdss->mdss_data;
169 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
170 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
172 if (data->ubwc_bank_spread)
175 if (data->ubwc_enc_version == UBWC_1_0)
178 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
183 const struct msm_mdss_data *data = msm_mdss->mdss_data;
184 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |
185 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
187 if (data->macrotile_mode)
190 if (data->ubwc_enc_version == UBWC_3_0)
193 if (data->ubwc_enc_version == UBWC_1_0)
196 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
201 const struct msm_mdss_data *data = msm_mdss->mdss_data;
202 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |
203 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);
205 if (data->ubwc_bank_spread)
208 if (data->macrotile_mode)
211 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);
213 if (data->ubwc_enc_version == UBWC_3_0) {
214 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
215 writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
217 if (data->ubwc_dec_version == UBWC_4_3)
218 writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
220 writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);
221 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);
238 static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
243 data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
247 hw_rev = readl_relaxed(mdss->mmio + REG_MDSS_HW_VERSION);
256 data->ubwc_dec_version = UBWC_1_0;
257 data->ubwc_enc_version = UBWC_1_0;
262 data->highest_bank_bit = 2;
264 data->highest_bank_bit = 1;
271 struct msm_mdss *mdss;
274 return ERR_PTR(-EINVAL);
276 mdss = dev_get_drvdata(dev);
282 if (!mdss->mdss_data && mdss->is_mdp5)
283 mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
285 return mdss->mdss_data;
294 * the interconnect is enabled (non-zero bandwidth). Let's make sure
297 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
298 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
300 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
301 icc_set_bw(msm_mdss->reg_bus_path, 0,
302 msm_mdss->mdss_data->reg_bus_bw);
304 icc_set_bw(msm_mdss->reg_bus_path, 0,
307 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
309 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
315 * mdss on mdp5 hardware. Skip it for now.
317 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
321 * ubwc config is part of the "mdss" region which is not accessible
327 switch (msm_mdss->mdss_data->ubwc_dec_version) {
343 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
344 msm_mdss->mdss_data->ubwc_dec_version);
345 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
346 readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));
347 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
348 readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));
359 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
361 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
362 icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
364 if (msm_mdss->reg_bus_path)
365 icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
372 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
375 pm_runtime_suspend(msm_mdss->dev);
376 pm_runtime_disable(msm_mdss->dev);
377 irq_domain_remove(msm_mdss->irq_controller.domain);
378 msm_mdss->irq_controller.domain = NULL;
393 "failed to acquire mdss reset\n");
410 * MDP5 MDSS uses at most three specified clocks.
420 return -EINVAL;
422 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
424 return -ENOMEM;
430 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
445 ret = msm_mdss_reset(&pdev->dev);
449 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
451 return ERR_PTR(-ENOMEM);
453 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
455 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
456 if (IS_ERR(msm_mdss->mmio))
457 return ERR_CAST(msm_mdss->mmio);
459 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
461 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
466 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
468 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
470 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
473 msm_mdss->num_clocks = ret;
474 msm_mdss->is_mdp5 = is_mdp5;
476 msm_mdss->dev = &pdev->dev;
489 pm_runtime_enable(&pdev->dev);
496 struct msm_mdss *mdss = dev_get_drvdata(dev);
500 return msm_mdss_disable(mdss);
505 struct msm_mdss *mdss = dev_get_drvdata(dev);
509 return msm_mdss_enable(mdss);
536 struct msm_mdss *mdss;
537 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
538 struct device *dev = &pdev->dev;
541 mdss = msm_mdss_init(pdev, is_mdp5);
542 if (IS_ERR(mdss))
543 return PTR_ERR(mdss);
545 platform_set_drvdata(pdev, mdss);
549 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
553 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
556 msm_mdss_destroy(mdss);
565 struct msm_mdss *mdss = platform_get_drvdata(pdev);
567 of_platform_depopulate(&pdev->dev);
569 msm_mdss_destroy(mdss);
737 { .compatible = "qcom,mdss" },
738 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
739 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
740 { .compatible = "qcom,sa8775p-mdss", .data = &sa8775p_data },
741 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
742 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
743 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
744 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
745 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
746 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
747 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
748 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
749 { .compatible = "qcom,sm6150-mdss", .data = &sm6150_data },
750 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
751 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
752 { .compatible = "qcom,sm7150-mdss", .data = &sm7150_data },
753 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
754 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
755 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
756 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
757 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
758 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
759 { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
768 .name = "msm-mdss",