2  * SPDX-License-Identifier: GPL-2.0
56 	path0 = devm_of_icc_get(dev, "mdp0-mem");  in msm_mdss_parse_data_bus_icc_path()
60 	msm_mdss->mdp_path[0] = path0;  in msm_mdss_parse_data_bus_icc_path()
61 	msm_mdss->num_mdp_paths = 1;  in msm_mdss_parse_data_bus_icc_path()
63 	path1 = devm_of_icc_get(dev, "mdp1-mem");  in msm_mdss_parse_data_bus_icc_path()
65 		msm_mdss->mdp_path[1] = path1;  in msm_mdss_parse_data_bus_icc_path()
66 		msm_mdss->num_mdp_paths++;  in msm_mdss_parse_data_bus_icc_path()
69 	reg_bus_path = of_icc_get(dev, "cpu-cfg");  in msm_mdss_parse_data_bus_icc_path()
71 		msm_mdss->reg_bus_path = reg_bus_path;  in msm_mdss_parse_data_bus_icc_path()
84 	interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS);  in msm_mdss_irq()
87 		irq_hw_number_t hwirq = fls(interrupts) - 1;  in msm_mdss_irq()
90 		rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,  in msm_mdss_irq()
93 			dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",  in msm_mdss_irq()
110 	clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);  in msm_mdss_irq_mask()
121 	set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);  in msm_mdss_irq_unmask()
137 	struct msm_mdss *msm_mdss = domain->host_data;  in msm_mdss_irqdomain_map()
155 	dev = msm_mdss->dev;  in _msm_mdss_irq_domain_add()
160 		return -EINVAL;  in _msm_mdss_irq_domain_add()
163 	msm_mdss->irq_controller.enabled_mask = 0;  in _msm_mdss_irq_domain_add()
164 	msm_mdss->irq_controller.domain = domain;  in _msm_mdss_irq_domain_add()
171 	const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_20()
172 	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |  in msm_mdss_setup_ubwc_dec_20()
173 		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);  in msm_mdss_setup_ubwc_dec_20()
175 	if (data->ubwc_bank_spread)  in msm_mdss_setup_ubwc_dec_20()
178 	if (data->ubwc_enc_version == UBWC_1_0)  in msm_mdss_setup_ubwc_dec_20()
181 	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_20()
186 	const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_30()
187 	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) |  in msm_mdss_setup_ubwc_dec_30()
188 		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);  in msm_mdss_setup_ubwc_dec_30()
190 	if (data->macrotile_mode)  in msm_mdss_setup_ubwc_dec_30()
193 	if (data->ubwc_enc_version == UBWC_3_0)  in msm_mdss_setup_ubwc_dec_30()
196 	if (data->ubwc_enc_version == UBWC_1_0)  in msm_mdss_setup_ubwc_dec_30()
199 	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_30()
204 	const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_40()
205 	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |  in msm_mdss_setup_ubwc_dec_40()
206 		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13);  in msm_mdss_setup_ubwc_dec_40()
208 	if (data->ubwc_bank_spread)  in msm_mdss_setup_ubwc_dec_40()
211 	if (data->macrotile_mode)  in msm_mdss_setup_ubwc_dec_40()
214 	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_40()
216 	if (data->ubwc_enc_version == UBWC_3_0) {  in msm_mdss_setup_ubwc_dec_40()
217 		writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
218 		writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);  in msm_mdss_setup_ubwc_dec_40()
220 		if (data->ubwc_dec_version == UBWC_4_3)  in msm_mdss_setup_ubwc_dec_40()
221 			writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
223 			writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_40()
224 		writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);  in msm_mdss_setup_ubwc_dec_40()
230 	const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data;  in msm_mdss_setup_ubwc_dec_50()
231 	u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) |  in msm_mdss_setup_ubwc_dec_50()
232 		    MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit);  in msm_mdss_setup_ubwc_dec_50()
234 	if (data->ubwc_bank_spread)  in msm_mdss_setup_ubwc_dec_50()
237 	if (data->macrotile_mode)  in msm_mdss_setup_ubwc_dec_50()
240 	writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC);  in msm_mdss_setup_ubwc_dec_50()
242 	writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2);  in msm_mdss_setup_ubwc_dec_50()
243 	writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE);  in msm_mdss_setup_ubwc_dec_50()
252 	 * the interconnect is enabled (non-zero bandwidth). Let's make sure  in msm_mdss_enable()
255 	for (i = 0; i < msm_mdss->num_mdp_paths; i++)  in msm_mdss_enable()
256 		icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));  in msm_mdss_enable()
258 	icc_set_bw(msm_mdss->reg_bus_path, 0,  in msm_mdss_enable()
259 		   msm_mdss->reg_bus_bw);  in msm_mdss_enable()
261 	ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);  in msm_mdss_enable()
263 		dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);  in msm_mdss_enable()
271 	if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)  in msm_mdss_enable()
281 	switch (msm_mdss->mdss_data->ubwc_dec_version) {  in msm_mdss_enable()
300 		dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",  in msm_mdss_enable()
301 			msm_mdss->mdss_data->ubwc_dec_version);  in msm_mdss_enable()
302 		dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",  in msm_mdss_enable()
303 			readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION));  in msm_mdss_enable()
304 		dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",  in msm_mdss_enable()
305 			readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION));  in msm_mdss_enable()
316 	clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);  in msm_mdss_disable()
318 	for (i = 0; i < msm_mdss->num_mdp_paths; i++)  in msm_mdss_disable()
319 		icc_set_bw(msm_mdss->mdp_path[i], 0, 0);  in msm_mdss_disable()
321 	if (msm_mdss->reg_bus_path)  in msm_mdss_disable()
322 		icc_set_bw(msm_mdss->reg_bus_path, 0, 0);  in msm_mdss_disable()
329 	struct platform_device *pdev = to_platform_device(msm_mdss->dev);  in msm_mdss_destroy()
332 	pm_runtime_suspend(msm_mdss->dev);  in msm_mdss_destroy()
333 	pm_runtime_disable(msm_mdss->dev);  in msm_mdss_destroy()
334 	irq_domain_remove(msm_mdss->irq_controller.domain);  in msm_mdss_destroy()
335 	msm_mdss->irq_controller.domain = NULL;  in msm_mdss_destroy()
377 		return -EINVAL;  in mdp5_mdss_parse_clock()
379 	bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);  in mdp5_mdss_parse_clock()
381 		return -ENOMEM;  in mdp5_mdss_parse_clock()
387 	ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);  in mdp5_mdss_parse_clock()
403 	ret = msm_mdss_reset(&pdev->dev);  in msm_mdss_init()
407 	msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);  in msm_mdss_init()
409 		return ERR_PTR(-ENOMEM);  in msm_mdss_init()
411 	msm_mdss->mdss_data = qcom_ubwc_config_get_data();  in msm_mdss_init()
412 	if (IS_ERR(msm_mdss->mdss_data))  in msm_mdss_init()
413 		return ERR_CAST(msm_mdss->mdss_data);  in msm_mdss_init()
415 	mdss_data = of_device_get_match_data(&pdev->dev);  in msm_mdss_init()
417 		return ERR_PTR(-EINVAL);  in msm_mdss_init()
419 	msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw;  in msm_mdss_init()
421 	msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");  in msm_mdss_init()
422 	if (IS_ERR(msm_mdss->mmio))  in msm_mdss_init()
423 		return ERR_CAST(msm_mdss->mmio);  in msm_mdss_init()
425 	dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio);  in msm_mdss_init()
427 	ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);  in msm_mdss_init()
432 		ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);  in msm_mdss_init()
434 		ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);  in msm_mdss_init()
436 		dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);  in msm_mdss_init()
439 	msm_mdss->num_clocks = ret;  in msm_mdss_init()
440 	msm_mdss->is_mdp5 = is_mdp5;  in msm_mdss_init()
442 	msm_mdss->dev = &pdev->dev;  in msm_mdss_init()
455 	pm_runtime_enable(&pdev->dev);  in msm_mdss_init()
503 	bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");  in mdss_probe()
504 	struct device *dev = &pdev->dev;  in mdss_probe()
514 	 * MDP5/DPU based devices don't have a flat hierarchy. There is a top  in mdss_probe()
515 	 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.  in mdss_probe()
516 	 * Populate the children devices, find the MDP5/DPU node, and then add  in mdss_probe()
519 	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);  in mdss_probe()
533 	of_platform_depopulate(&pdev->dev);  in mdss_remove()
556 	{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
557 	{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
558 	{ .compatible = "qcom,sa8775p-mdss", .data = &data_74k },
559 	{ .compatible = "qcom,sar2130p-mdss", .data = &data_74k },
560 	{ .compatible = "qcom,sdm670-mdss", .data = &data_76k8 },
561 	{ .compatible = "qcom,sdm845-mdss", .data = &data_76k8 },
562 	{ .compatible = "qcom,sc7180-mdss", .data = &data_76k8 },
563 	{ .compatible = "qcom,sc7280-mdss", .data = &data_74k },
564 	{ .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 },
565 	{ .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 },
566 	{ .compatible = "qcom,sm6115-mdss", .data = &data_76k8 },
567 	{ .compatible = "qcom,sm6125-mdss", .data = &data_76k8 },
568 	{ .compatible = "qcom,sm6150-mdss", .data = &data_76k8 },
569 	{ .compatible = "qcom,sm6350-mdss", .data = &data_76k8 },
570 	{ .compatible = "qcom,sm6375-mdss", .data = &data_76k8 },
571 	{ .compatible = "qcom,sm7150-mdss", .data = &data_76k8 },
572 	{ .compatible = "qcom,sm8150-mdss", .data = &data_76k8 },
573 	{ .compatible = "qcom,sm8250-mdss", .data = &data_76k8 },
574 	{ .compatible = "qcom,sm8350-mdss", .data = &data_74k },
575 	{ .compatible = "qcom,sm8450-mdss", .data = &data_74k },
576 	{ .compatible = "qcom,sm8550-mdss", .data = &data_57k },
577 	{ .compatible = "qcom,sm8650-mdss", .data = &data_57k },
578 	{ .compatible = "qcom,sm8750-mdss", .data = &data_57k },
580 	{ .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 },
589 		.name   = "msm-mdss",