1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/adreno-smmu-priv.h>
116  * struct msm_gpu_devfreq - devfreq related state
159 	 * Used to delay clamping to idle freq on active->idle transition.
187 		bool active;  member
210 	 * TODO move to per-ring locking where feasible (ie. submit/retire
219 	 * determine transitions between active and idle.
225 	/** lock: protects active_submits and idle/active transitions */
263 	/* work for handling active-list retiring: */
284 	 * switch-over happened early enough in mesa a6xx bringup that we
305 	struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(&gpu->pdev->dev);  in adreno_smmu_has_prr()
310 	return adreno_smmu && adreno_smmu->set_prr_addr;  in adreno_smmu_has_prr()
325 	for (i = 0; i < gpu->nr_rings; i++) {  in msm_gpu_active()
326 		struct msm_ringbuffer *ring = gpu->rb[i];  in msm_gpu_active()
328 		if (fence_after(ring->fctx->last_fence, ring->memptrs->fence))  in msm_gpu_active()
335 /* Perf-Counters:
353 #define NR_SCHED_PRIORITIES (1 + DRM_SCHED_PRIORITY_LOW - DRM_SCHED_PRIORITY_HIGH)
356  * struct msm_context - per-drm_file context
377 	 * to the ring buffer are no-op'd.
384 	 * Has userspace opted-in to userspace managed VM (ie. VM_BIND) via
392 	 * The per-process GPU address-space.  Do not access directly, use
403 	 * A unique per-process sequence number.  Used to detect context
414 	 * pps-producer (perfetto), and restricted to CAP_SYS_ADMIN.
460 	 * Table of per-priority-level sched entities used by submitqueues
465 	 * create at most one &drm_sched_entity per-process per-priority-
482  * msm_context_is_vm_bind() - has userspace opted in to VM_BIND?
494 	return ctx->userspace_managed_vm;  in msm_context_is_vmbind()
498  * msm_gpu_convert_priority - Map userspace priority to ring # and sched priority
515  *   sched_prio = NR_SCHED_PRIORITIES -
516  *                (userspace_prio % NR_SCHED_PRIORITIES) - 1
529 	/* invert sched priority to map to higher-numeric-is-higher-  in msm_gpu_convert_priority()
532 	sp = NR_SCHED_PRIORITIES - sp - 1;  in msm_gpu_convert_priority()
534 	if (rn >= gpu->nr_rings)  in msm_gpu_convert_priority()
535 		return -EINVAL;  in msm_gpu_convert_priority()
544  * struct msm_gpu_submitqueues - Userspace created context.
557  * @ctx:       the per-drm_file context associated with the submitqueue (ie.
561  * @fence_idr: maps fence-id to dma_fence for userspace visible fence
566  * @entity:    the submit job-queue
630 	writel(data, gpu->mmio + (reg << 2));  in gpu_write()
636 	return readl(gpu->mmio + (reg << 2));  in gpu_read()
642 	msm_rmw(gpu->mmio + (reg << 2), mask, or);  in gpu_rmw()
664 	val = (u64) readl(gpu->mmio + (reg << 2));  in gpu_read64()
666 	val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);  in gpu_read64()
675 	writel(lower_32_bits(val), gpu->mmio + (reg << 2));  in gpu_write64()
677 	writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));  in gpu_write64()
704 	kref_put(&ctx->ref, __msm_context_destroy);  in msm_context_put()
710 	kref_get(&ctx->ref);  in msm_context_get()
750 		kref_put(&queue->ref, msm_submitqueue_destroy);  in msm_submitqueue_put()
757 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_get()
759 	if (gpu->crashstate) {  in msm_gpu_crashstate_get()
760 		kref_get(&gpu->crashstate->ref);  in msm_gpu_crashstate_get()
761 		state = gpu->crashstate;  in msm_gpu_crashstate_get()
764 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_get()
771 	mutex_lock(&gpu->lock);  in msm_gpu_crashstate_put()
773 	if (gpu->crashstate) {  in msm_gpu_crashstate_put()
774 		if (gpu->funcs->gpu_state_put(gpu->crashstate))  in msm_gpu_crashstate_put()
775 			gpu->crashstate = NULL;  in msm_gpu_crashstate_put()
778 	mutex_unlock(&gpu->lock);  in msm_gpu_crashstate_put()
784  * Simple macro to semi-cleanly add the MAP_PRIV flag for targets that can
788 	(((gpu)->hw_apriv ? MSM_BO_MAP_PRIV : 0) | (flags))