14 #define S_DIV_ROUND_UP(n, d)	\  argument
15 	(((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
133 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc()
137 	DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc()
172 	timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;  in msm_dsi_dphy_timing_calc_v2()
181 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v2()
189 	temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;  in msm_dsi_dphy_timing_calc_v2()
190 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;  in msm_dsi_dphy_timing_calc_v2()
194 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v2()
196 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v2()
205 	temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;  in msm_dsi_dphy_timing_calc_v2()
206 	tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;  in msm_dsi_dphy_timing_calc_v2()
210 	tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v2()
212 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v2()
231 	temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;  in msm_dsi_dphy_timing_calc_v2()
232 	temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;  in msm_dsi_dphy_timing_calc_v2()
233 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :  in msm_dsi_dphy_timing_calc_v2()
234 				(((timing->hs_rqst_ckln << 3) + 8) * ui);  in msm_dsi_dphy_timing_calc_v2()
247 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc_v2()
251 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v2()
289 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v3()
297 	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
302 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v3()
304 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v3()
313 	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
339 	temp = 8 * ui + (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v3()
340 	temp += (((timing->clk_zero + 3) << 3) + 11) * ui;  in msm_dsi_dphy_timing_calc_v3()
341 	temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :  in msm_dsi_dphy_timing_calc_v3()
342 		(((timing->hs_rqst_ckln << 3) + 8) * ui);  in msm_dsi_dphy_timing_calc_v3()
357 	timing->ta_go = 3;  in msm_dsi_dphy_timing_calc_v3()
361 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v3()
397 	ui_x8 = ui << 3;  in msm_dsi_dphy_timing_calc_v4()
410 	temp = 300 * coeff - (timing->clk_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v4()
415 	tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);  in msm_dsi_dphy_timing_calc_v4()
417 	tmax = (temp + 3 * ui) / ui_x8;  in msm_dsi_dphy_timing_calc_v4()
426 	temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;  in msm_dsi_dphy_timing_calc_v4()
463 	DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",  in msm_dsi_dphy_timing_calc_v4()
509 	DBG("%d, %d, %d, %d, %d",  in msm_dsi_cphy_timing_calc_v4()
578 	{ .compatible = "qcom,sm8750-dsi-phy-3nm",
746 		DRM_DEV_ERROR(dev, "%s: resume failed, %d\n",  in msm_dsi_phy_enable()
753 		DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",  in msm_dsi_phy_enable()
760 		DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);  in msm_dsi_phy_enable()
776 			DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n",  in msm_dsi_phy_enable()