Lines Matching +full:0 +full:x00000010
13 #define REG_DP_HW_VERSION (0x00000000)
14 #define DP_HW_VERSION_1_0 0x10000000
15 #define DP_HW_VERSION_1_2 0x10020000
17 #define REG_DP_SW_RESET (0x00000010)
18 #define DP_SW_RESET (0x00000001)
20 #define REG_DP_PHY_CTRL (0x00000014)
21 #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001)
22 #define DP_PHY_CTRL_SW_RESET (0x00000004)
24 #define REG_DP_CLK_CTRL (0x00000018)
25 #define REG_DP_CLK_ACTIVE (0x0000001C)
27 #define REG_DP_INTR_STATUS (0x00000020)
28 #define DP_INTR_HPD BIT(0)
39 #define REG_DP_INTR_STATUS2 (0x00000024)
40 #define DP_INTR_READY_FOR_VIDEO BIT(0)
45 #define REG_DP_INTR_STATUS3 (0x00000028)
47 #define REG_DP_INTR_STATUS4 (0x0000002C)
48 #define PSR_UPDATE_INT (0x00000001)
49 #define PSR_CAPTURE_INT (0x00000004)
50 #define PSR_EXIT_INT (0x00000010)
51 #define PSR_UPDATE_ERROR_INT (0x00000040)
52 #define PSR_WAKE_ERROR_INT (0x00000100)
54 #define REG_DP_INTR_MASK4 (0x00000030)
55 #define PSR_UPDATE_MASK (0x00000001)
56 #define PSR_CAPTURE_MASK (0x00000002)
57 #define PSR_EXIT_MASK (0x00000004)
58 #define PSR_UPDATE_ERROR_MASK (0x00000008)
59 #define PSR_WAKE_ERROR_MASK (0x00000010)
61 #define REG_DP_DP_HPD_CTRL (0x00000000)
62 #define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
64 #define REG_DP_DP_HPD_INT_STATUS (0x00000004)
66 #define REG_DP_DP_HPD_INT_ACK (0x00000008)
67 #define DP_DP_HPD_PLUG_INT_ACK (0x00000001)
68 #define DP_DP_IRQ_HPD_INT_ACK (0x00000002)
69 #define DP_DP_HPD_REPLUG_INT_ACK (0x00000004)
70 #define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008)
71 #define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F)
72 #define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C)
74 #define REG_DP_DP_HPD_INT_MASK (0x0000000C)
75 #define DP_DP_HPD_PLUG_INT_MASK (0x00000001)
76 #define DP_DP_IRQ_HPD_INT_MASK (0x00000002)
77 #define DP_DP_HPD_REPLUG_INT_MASK (0x00000004)
78 #define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008)
83 #define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000)
84 #define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000)
85 #define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000)
86 #define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000)
88 #define REG_DP_DP_HPD_REFTIMER (0x00000018)
91 #define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C)
92 #define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020)
93 #define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA)
94 #define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0)
96 #define REG_DP_AUX_CTRL (0x00000030)
97 #define DP_AUX_CTRL_ENABLE (0x00000001)
98 #define DP_AUX_CTRL_RESET (0x00000002)
100 #define REG_DP_AUX_DATA (0x00000034)
101 #define DP_AUX_DATA_READ (0x00000001)
102 #define DP_AUX_DATA_WRITE (0x00000000)
103 #define DP_AUX_DATA_OFFSET (0x00000008)
104 #define DP_AUX_DATA_INDEX_OFFSET (0x00000010)
105 #define DP_AUX_DATA_MASK (0x0000ff00)
106 #define DP_AUX_DATA_INDEX_WRITE (0x80000000)
108 #define REG_DP_AUX_TRANS_CTRL (0x00000038)
109 #define DP_AUX_TRANS_CTRL_I2C (0x00000100)
110 #define DP_AUX_TRANS_CTRL_GO (0x00000200)
111 #define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400)
112 #define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800)
114 #define REG_DP_TIMEOUT_COUNT (0x0000003C)
115 #define REG_DP_AUX_LIMITS (0x00000040)
116 #define REG_DP_AUX_STATUS (0x00000044)
118 #define DP_DPCD_CP_IRQ (0x201)
119 #define DP_DPCD_RXSTATUS (0x69493)
121 #define DP_INTERRUPT_TRANS_NUM (0x000000A0)
123 #define REG_DP_MAINLINK_CTRL (0x00000000)
124 #define DP_MAINLINK_CTRL_ENABLE (0x00000001)
125 #define DP_MAINLINK_CTRL_RESET (0x00000002)
126 #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010)
130 #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000)
132 #define REG_DP_STATE_CTRL (0x00000004)
133 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001)
134 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002)
135 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004)
136 #define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008)
137 #define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010)
138 #define DP_STATE_CTRL_LINK_PRBS7 (0x00000020)
139 #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040)
140 #define DP_STATE_CTRL_SEND_VIDEO (0x00000080)
141 #define DP_STATE_CTRL_PUSH_IDLE (0x00000100)
143 #define REG_DP_CONFIGURATION_CTRL (0x00000008)
144 #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001)
145 #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002)
146 #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004)
147 #define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008)
148 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010)
149 #define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040)
150 #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080)
151 #define DP_CONFIGURATION_CTRL_BPC (0x00000100)
152 #define DP_CONFIGURATION_CTRL_ASSR (0x00000400)
153 #define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800)
154 #define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000)
155 #define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04)
156 #define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08)
157 #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D)
159 #define REG_DP_SOFTWARE_MVID (0x00000010)
160 #define REG_DP_SOFTWARE_NVID (0x00000018)
161 #define REG_DP_TOTAL_HOR_VER (0x0000001C)
162 #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020)
163 #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024)
164 #define REG_DP_ACTIVE_HOR_VER (0x00000028)
166 #define REG_DP_MISC1_MISC0 (0x0000002C)
167 #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001)
168 #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001)
169 #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005)
170 #define DP_MISC1_VSC_SDP (0x00004000)
172 #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0)
173 #define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04)
175 #define REG_DP_VALID_BOUNDARY (0x00000030)
176 #define REG_DP_VALID_BOUNDARY_2 (0x00000034)
178 #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038)
179 #define LANE0_MAPPING_SHIFT (0x00000000)
180 #define LANE1_MAPPING_SHIFT (0x00000002)
181 #define LANE2_MAPPING_SHIFT (0x00000004)
182 #define LANE3_MAPPING_SHIFT (0x00000006)
184 #define REG_DP_MAINLINK_READY (0x00000040)
185 #define DP_MAINLINK_READY_FOR_VIDEO (0x00000001)
186 #define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003)
188 #define REG_DP_MAINLINK_LEVELS (0x00000044)
189 #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002)
192 #define REG_DP_TU (0x0000004C)
194 #define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054)
195 #define DP_HBR2_ERM_PATTERN (0x00010000)
197 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0)
198 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4)
199 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8)
201 #define MMSS_DP_MISC1_MISC0 (0x0000002C)
202 #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080)
203 #define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084)
204 #define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088)
205 #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C)
206 #define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090)
207 #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
208 #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
210 #define REG_PSR_CONFIG (0x00000100)
211 #define DISABLE_PSR (0x00000000)
212 #define PSR1_SUPPORTED (0x00000001)
213 #define PSR2_WITHOUT_FRAMESYNC (0x00000002)
214 #define PSR2_WITH_FRAMESYNC (0x00000003)
216 #define REG_PSR_CMD (0x00000110)
217 #define PSR_ENTER (0x00000001)
218 #define PSR_EXIT (0x00000002)
220 #define MMSS_DP_PSR_CRC_RG (0x00000154)
221 #define MMSS_DP_PSR_CRC_B (0x00000158)
223 #define REG_DP_COMPRESSION_MODE_CTRL (0x00000180)
225 #define MMSS_DP_AUDIO_CFG (0x00000200)
226 #define MMSS_DP_AUDIO_STATUS (0x00000204)
227 #define MMSS_DP_AUDIO_PKT_CTRL (0x00000208)
228 #define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C)
229 #define MMSS_DP_AUDIO_ACR_CTRL (0x00000210)
230 #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214)
232 #define MMSS_DP_SDP_CFG (0x00000228)
233 #define GEN0_SDP_EN (0x00020000)
234 #define MMSS_DP_SDP_CFG2 (0x0000022C)
235 #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230)
236 #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234)
237 #define GENERIC0_SDPSIZE_VALID (0x00010000)
239 #define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
240 #define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
242 #define MMSS_DP_SDP_CFG3 (0x0000024c)
243 #define UPDATE_SDP (0x00000001)
245 #define MMSS_DP_EXTENSION_0 (0x00000250)
246 #define MMSS_DP_EXTENSION_1 (0x00000254)
247 #define MMSS_DP_EXTENSION_2 (0x00000258)
248 #define MMSS_DP_EXTENSION_3 (0x0000025C)
249 #define MMSS_DP_EXTENSION_4 (0x00000260)
250 #define MMSS_DP_EXTENSION_5 (0x00000264)
251 #define MMSS_DP_EXTENSION_6 (0x00000268)
252 #define MMSS_DP_EXTENSION_7 (0x0000026C)
253 #define MMSS_DP_EXTENSION_8 (0x00000270)
254 #define MMSS_DP_EXTENSION_9 (0x00000274)
255 #define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278)
256 #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C)
257 #define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280)
258 #define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284)
259 #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288)
260 #define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C)
261 #define MMSS_DP_AUDIO_ISRC_0 (0x00000290)
262 #define MMSS_DP_AUDIO_ISRC_1 (0x00000294)
263 #define MMSS_DP_AUDIO_ISRC_2 (0x00000298)
264 #define MMSS_DP_AUDIO_ISRC_3 (0x0000029C)
265 #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0)
266 #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4)
267 #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8)
268 #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC)
269 #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0)
271 #define MMSS_DP_GENERIC0_0 (0x00000300)
272 #define MMSS_DP_GENERIC0_1 (0x00000304)
273 #define MMSS_DP_GENERIC0_2 (0x00000308)
274 #define MMSS_DP_GENERIC0_3 (0x0000030C)
275 #define MMSS_DP_GENERIC0_4 (0x00000310)
276 #define MMSS_DP_GENERIC0_5 (0x00000314)
277 #define MMSS_DP_GENERIC0_6 (0x00000318)
278 #define MMSS_DP_GENERIC0_7 (0x0000031C)
279 #define MMSS_DP_GENERIC0_8 (0x00000320)
280 #define MMSS_DP_GENERIC0_9 (0x00000324)
281 #define MMSS_DP_GENERIC1_0 (0x00000328)
282 #define MMSS_DP_GENERIC1_1 (0x0000032C)
283 #define MMSS_DP_GENERIC1_2 (0x00000330)
284 #define MMSS_DP_GENERIC1_3 (0x00000334)
285 #define MMSS_DP_GENERIC1_4 (0x00000338)
286 #define MMSS_DP_GENERIC1_5 (0x0000033C)
287 #define MMSS_DP_GENERIC1_6 (0x00000340)
288 #define MMSS_DP_GENERIC1_7 (0x00000344)
289 #define MMSS_DP_GENERIC1_8 (0x00000348)
290 #define MMSS_DP_GENERIC1_9 (0x0000034C)
292 #define MMSS_DP_VSCEXT_0 (0x000002D0)
293 #define MMSS_DP_VSCEXT_1 (0x000002D4)
294 #define MMSS_DP_VSCEXT_2 (0x000002D8)
295 #define MMSS_DP_VSCEXT_3 (0x000002DC)
296 #define MMSS_DP_VSCEXT_4 (0x000002E0)
297 #define MMSS_DP_VSCEXT_5 (0x000002E4)
298 #define MMSS_DP_VSCEXT_6 (0x000002E8)
299 #define MMSS_DP_VSCEXT_7 (0x000002EC)
300 #define MMSS_DP_VSCEXT_8 (0x000002F0)
301 #define MMSS_DP_VSCEXT_9 (0x000002F4)
303 #define MMSS_DP_BIST_ENABLE (0x00000000)
304 #define DP_BIST_ENABLE_DPBIST_EN (0x00000001)
306 #define MMSS_DP_TIMING_ENGINE_EN (0x00000010)
307 #define DP_TIMING_ENGINE_EN_EN (0x00000001)
309 #define MMSS_DP_INTF_CONFIG (0x00000014)
310 #define MMSS_DP_INTF_HSYNC_CTL (0x00000018)
311 #define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C)
312 #define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020)
313 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024)
314 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028)
315 #define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C)
316 #define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030)
317 #define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034)
318 #define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038)
319 #define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C)
320 #define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040)
321 #define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044)
322 #define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048)
323 #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C)
324 #define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050)
325 #define MMSS_DP_INTF_POLARITY_CTL (0x00000058)
327 #define MMSS_DP_TPG_MAIN_CONTROL (0x00000060)
328 #define MMSS_DP_DSC_DTO (0x0000007C)
329 #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100)
331 #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064)
332 #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001)
333 #define DP_TPG_VIDEO_CONFIG_RGB (0x00000004)
335 #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)
337 #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C)
338 #define REG_DP_PHY_AUX_BIST_CFG (0x00000050)
339 #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC)
342 #define DP_HDCP_CTRL (0x0A0)
343 #define DP_HDCP_STATUS (0x0A4)
344 #define DP_HDCP_SW_UPPER_AKSV (0x098)
345 #define DP_HDCP_SW_LOWER_AKSV (0x09C)
346 #define DP_HDCP_ENTROPY_CTRL0 (0x350)
347 #define DP_HDCP_ENTROPY_CTRL1 (0x35C)
348 #define DP_HDCP_SHA_STATUS (0x0C8)
349 #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0)
350 #define DP_HDCP_RCVPORT_DATA3 (0x0A4)
351 #define DP_HDCP_RCVPORT_DATA4 (0x0A8)
352 #define DP_HDCP_RCVPORT_DATA5 (0x0C0)
353 #define DP_HDCP_RCVPORT_DATA6 (0x0C4)
355 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024)
356 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028)
357 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004)
358 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008)
359 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C)
360 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010)
361 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014)
362 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018)
363 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C)
364 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020)