Lines Matching full:ctrl
145 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset)
147 return readl_relaxed(ctrl->ahb_base + offset);
150 static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl,
157 writel(data, ctrl->ahb_base + offset);
160 static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset)
162 return readl_relaxed(ctrl->link_base + offset);
165 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl,
172 writel(data, ctrl->link_base + offset);
199 struct msm_dp_ctrl_private *ctrl =
203 sw_reset = msm_dp_read_ahb(ctrl, REG_DP_SW_RESET);
206 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset);
210 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset);
212 if (!ctrl->hw_revision) {
213 ctrl->hw_revision = msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION);
214 ctrl->panel->hw_revision = ctrl->hw_revision;
218 static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl)
222 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS);
226 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS,
233 static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl)
237 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS2);
241 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2,
249 struct msm_dp_ctrl_private *ctrl =
252 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS,
254 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2,
260 struct msm_dp_ctrl_private *ctrl =
263 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00);
264 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00);
267 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl)
271 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS4);
274 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack);
279 static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *ctrl)
281 msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
284 static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl)
288 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
290 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val);
293 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl)
297 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
299 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val);
302 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl)
306 drm_dbg_dp(ctrl->drm_dev, "enable\n");
308 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
312 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
315 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
318 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
322 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
325 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl)
329 drm_dbg_dp(ctrl->drm_dev, "disable\n");
331 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
333 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
336 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl)
340 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
342 if (ctrl->hw_revision >= DP_HW_VERSION_1_2)
347 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
350 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl)
356 ret = readl_poll_timeout(ctrl->link_base + REG_DP_MAINLINK_READY,
369 struct msm_dp_ctrl_private *ctrl;
371 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
373 reinit_completion(&ctrl->idle_comp);
374 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE);
376 if (!wait_for_completion_timeout(&ctrl->idle_comp,
380 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n");
383 static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl)
386 const u8 *dpcd = ctrl->panel->dpcd;
391 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
398 tbd = msm_dp_link_get_test_bits_depth(ctrl->link,
399 ctrl->panel->msm_dp_mode.bpp);
404 config |= ((ctrl->link->link_params.num_lanes - 1)
416 if (ctrl->panel->psr_cap.version)
419 drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config);
421 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config);
424 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl)
434 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING,
438 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl)
442 msm_dp_ctrl_lane_mapping(ctrl);
443 msm_dp_setup_peripheral_flush(ctrl);
445 msm_dp_ctrl_config_ctrl(ctrl);
447 test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp);
448 colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link);
450 misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0);
459 drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val);
460 msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val);
462 msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en);
897 static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl,
982 drm_dbg_dp(ctrl->drm_dev,
1018 drm_dbg_dp(ctrl->drm_dev,
1213 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n",
1215 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n",
1217 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n",
1219 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n",
1221 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n",
1223 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n",
1225 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n",
1231 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl,
1237 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode;
1239 in.lclk = ctrl->link->link_params.rate / 1000;
1243 in.nlanes = ctrl->link->link_params.num_lanes;
1244 in.bpp = ctrl->panel->msm_dp_mode.bpp;
1245 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444;
1252 _dp_ctrl_calc_tu(ctrl, &in, tu_table);
1255 static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl)
1262 msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table);
1278 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary);
1279 msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu);
1280 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2);
1283 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl)
1287 if (!wait_for_completion_timeout(&ctrl->video_comp,
1295 static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl,
1298 union phy_configure_opts *phy_opts = &ctrl->phy_opts;
1304 phy_configure(ctrl->phy, phy_opts);
1310 static int msm_dp_ctrl_update_phy_vx_px(struct msm_dp_ctrl_private *ctrl,
1313 struct msm_dp_link *link = ctrl->link;
1321 drm_dbg_dp(ctrl->drm_dev,
1324 ret = msm_dp_ctrl_set_vx_px(ctrl,
1331 drm_dbg_dp(ctrl->drm_dev,
1338 drm_dbg_dp(ctrl->drm_dev,
1346 lane_cnt = ctrl->link->link_params.num_lanes;
1351 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n",
1359 ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt);
1366 static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl,
1373 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern);
1385 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf);
1389 static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl,
1396 drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit);
1397 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit);
1402 ret = readx_poll_timeout(readl, ctrl->link_base + REG_DP_MAINLINK_READY,
1413 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl,
1421 delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux,
1422 ctrl->panel->dpcd, dp_phy, false);
1424 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
1428 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, 1);
1431 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
1434 msm_dp_link_reset_phy_params_vx_px(ctrl->link);
1435 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy);
1440 old_v_level = ctrl->link->phy_params.v_level;
1444 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status);
1449 ctrl->link->link_params.num_lanes)) {
1453 if (ctrl->link->phy_params.v_level >=
1459 if (old_v_level != ctrl->link->phy_params.v_level) {
1461 old_v_level = ctrl->link->phy_params.v_level;
1464 msm_dp_link_adjust_levels(ctrl->link, link_status);
1465 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy);
1474 static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl)
1478 switch (ctrl->link->link_params.rate) {
1480 ctrl->link->link_params.rate = 540000;
1483 ctrl->link->link_params.rate = 270000;
1486 ctrl->link->link_params.rate = 162000;
1495 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n",
1496 ctrl->link->link_params.rate);
1502 static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl)
1505 if (ctrl->link->link_params.num_lanes == 1)
1508 ctrl->link->link_params.num_lanes /= 2;
1509 ctrl->link->link_params.rate = ctrl->panel->link_info.rate;
1511 ctrl->link->phy_params.p_level = 0;
1512 ctrl->link->phy_params.v_level = 0;
1517 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl,
1522 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy);
1524 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux,
1525 ctrl->panel->dpcd, dp_phy, false);
1529 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl,
1539 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux,
1540 ctrl->panel->dpcd, dp_phy, false);
1542 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
1546 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) {
1549 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) {
1557 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit);
1561 msm_dp_ctrl_train_pattern_set(ctrl, pattern, dp_phy);
1566 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status);
1571 ctrl->link->link_params.num_lanes)) {
1575 msm_dp_link_adjust_levels(ctrl->link, link_status);
1576 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy);
1585 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl,
1590 ret = msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy);
1595 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy);
1597 ret = msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy);
1602 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy);
1607 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl,
1612 const u8 *dpcd = ctrl->panel->dpcd;
1617 msm_dp_ctrl_config_ctrl(ctrl);
1619 link_info.num_lanes = ctrl->link->link_params.num_lanes;
1620 link_info.rate = ctrl->link->link_params.rate;
1623 msm_dp_aux_link_configure(ctrl->aux, &link_info);
1629 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);
1633 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,
1637 for (i = ctrl->link->lttpr_count - 1; i >= 0; i--) {
1640 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy);
1641 msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy);
1652 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX);
1659 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
1664 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl,
1669 msm_dp_ctrl_mainlink_enable(ctrl);
1671 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
1680 ret = msm_dp_ctrl_link_train(ctrl, training_step);
1687 struct msm_dp_ctrl_private *ctrl;
1690 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1692 if (ctrl->core_clks_on) {
1693 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n");
1697 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks);
1701 ctrl->core_clks_on = true;
1703 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n");
1704 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1705 str_on_off(ctrl->stream_clks_on),
1706 str_on_off(ctrl->link_clks_on),
1707 str_on_off(ctrl->core_clks_on));
1714 struct msm_dp_ctrl_private *ctrl;
1716 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1718 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks);
1720 ctrl->core_clks_on = false;
1722 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n");
1723 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1724 str_on_off(ctrl->stream_clks_on),
1725 str_on_off(ctrl->link_clks_on),
1726 str_on_off(ctrl->core_clks_on));
1731 struct msm_dp_ctrl_private *ctrl;
1734 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1736 if (ctrl->link_clks_on) {
1737 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n");
1741 if (!ctrl->core_clks_on) {
1742 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n");
1747 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks);
1751 ctrl->link_clks_on = true;
1753 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n");
1754 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1755 str_on_off(ctrl->stream_clks_on),
1756 str_on_off(ctrl->link_clks_on),
1757 str_on_off(ctrl->core_clks_on));
1764 struct msm_dp_ctrl_private *ctrl;
1766 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1768 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks);
1770 ctrl->link_clks_on = false;
1772 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n");
1773 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n",
1774 str_on_off(ctrl->stream_clks_on),
1775 str_on_off(ctrl->link_clks_on),
1776 str_on_off(ctrl->core_clks_on));
1779 static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl)
1782 struct phy *phy = ctrl->phy;
1783 const u8 *dpcd = ctrl->panel->dpcd;
1785 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1786 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100;
1787 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd);
1789 phy_configure(phy, &ctrl->phy_opts);
1792 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
1793 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl);
1797 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
1802 static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl)
1805 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP);
1806 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0);
1809 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl)
1813 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD);
1818 msm_dp_ctrl_enable_sdp(ctrl);
1819 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd);
1822 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl)
1826 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD);
1831 msm_dp_ctrl_enable_sdp(ctrl);
1832 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd);
1837 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl,
1841 if (!ctrl->panel->psr_cap.version)
1845 cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG);
1847 msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg);
1849 msm_dp_ctrl_config_psr_interrupt(ctrl);
1850 msm_dp_ctrl_enable_sdp(ctrl);
1853 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);
1858 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl,
1861 if (!ctrl->panel->psr_cap.version)
1875 reinit_completion(&ctrl->psr_op_comp);
1876 msm_dp_ctrl_psr_enter(ctrl);
1878 if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
1881 msm_dp_ctrl_psr_exit(ctrl);
1886 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
1888 msm_dp_ctrl_psr_mainlink_disable(ctrl);
1890 msm_dp_ctrl_psr_mainlink_enable(ctrl);
1892 msm_dp_ctrl_psr_exit(ctrl);
1893 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
1894 msm_dp_ctrl_wait4video_ready(ctrl);
1895 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0);
1899 static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl)
1901 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL,
1904 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0);
1909 struct msm_dp_ctrl_private *ctrl;
1912 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1913 phy = ctrl->phy;
1915 msm_dp_ctrl_phy_reset(ctrl);
1918 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1924 struct msm_dp_ctrl_private *ctrl;
1927 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
1928 phy = ctrl->phy;
1930 msm_dp_ctrl_phy_reset(ctrl);
1932 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1936 static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl)
1938 struct phy *phy = ctrl->phy;
1941 msm_dp_ctrl_mainlink_disable(ctrl);
1942 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1943 phy_configure(phy, &ctrl->phy_opts);
1949 dev_pm_opp_set_rate(ctrl->dev, 0);
1951 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
1957 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
1966 static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl)
1970 phy = ctrl->phy;
1972 msm_dp_ctrl_mainlink_disable(ctrl);
1974 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl);
1976 dev_pm_opp_set_rate(ctrl->dev, 0);
1977 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
1985 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
1990 static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl)
1995 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl);
1997 ctrl->link->phy_params.p_level = 0;
1998 ctrl->link->phy_params.v_level = 0;
2000 ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step);
2004 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX);
2006 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
2008 ret = msm_dp_ctrl_wait4video_ready(ctrl);
2015 static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl,
2021 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0);
2023 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern);
2026 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2032 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
2035 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
2037 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS,
2039 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2044 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2049 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2052 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0,
2055 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1,
2058 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2,
2063 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
2065 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value);
2068 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
2071 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET,
2073 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS,
2075 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2077 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL);
2079 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value);
2083 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL,
2085 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL,
2090 drm_dbg_dp(ctrl->drm_dev,
2096 static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl)
2100 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel;
2102 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
2104 if (msm_dp_ctrl_set_vx_px(ctrl,
2105 ctrl->link->phy_params.v_level,
2106 ctrl->link->phy_params.p_level)) {
2110 msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested);
2111 msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX);
2112 msm_dp_link_send_test_response(ctrl->link);
2114 pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY);
2143 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n",
2148 static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl)
2153 if (!ctrl->link->phy_params.phy_test_pattern_sel) {
2154 drm_dbg_dp(ctrl->drm_dev,
2164 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl);
2166 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl);
2172 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock;
2173 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
2179 if (ctrl->stream_clks_on) {
2180 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
2182 ret = clk_prepare_enable(ctrl->pixel_clk);
2187 ctrl->stream_clks_on = true;
2190 msm_dp_ctrl_send_phy_test_pattern(ctrl);
2197 struct msm_dp_ctrl_private *ctrl;
2205 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2206 sink_request = ctrl->link->sink_request;
2209 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n");
2210 if (msm_dp_ctrl_process_phy_test_request(ctrl)) {
2217 if (msm_dp_ctrl_link_maintenance(ctrl)) {
2224 msm_dp_link_send_test_response(ctrl->link);
2225 if (msm_dp_ctrl_link_maintenance(ctrl)) {
2251 static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl)
2254 int num_lanes = ctrl->link->link_params.num_lanes;
2256 drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
2264 struct msm_dp_ctrl_private *ctrl;
2275 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2277 rate = ctrl->panel->link_info.rate;
2278 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock;
2280 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl);
2282 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
2283 drm_dbg_dp(ctrl->drm_dev,
2288 ctrl->link->link_params.rate = rate;
2289 ctrl->link->link_params.num_lanes =
2290 ctrl->panel->link_info.num_lanes;
2291 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
2295 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
2296 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
2299 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
2305 rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step);
2311 if (!msm_dp_aux_is_link_connected(ctrl->aux))
2314 drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
2316 rc = msm_dp_ctrl_link_rate_down_shift(ctrl);
2319 ctrl->link->link_params.num_lanes)) {
2324 rc = msm_dp_ctrl_link_lane_down_shift(ctrl);
2336 if (!msm_dp_aux_is_link_connected(ctrl->aux))
2339 drm_dp_dpcd_read_link_status(ctrl->aux, link_status);
2342 ctrl->link->link_params.num_lanes))
2343 rc = msm_dp_ctrl_link_rate_down_shift(ctrl);
2345 rc = msm_dp_ctrl_link_lane_down_shift(ctrl);
2353 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX);
2356 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl);
2363 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN)
2377 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX);
2379 msm_dp_ctrl_deinitialize_mainlink(ctrl);
2386 static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl)
2390 return msm_dp_ctrl_setup_main_link(ctrl, &training_step);
2393 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl,
2444 drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid);
2445 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid);
2446 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid);
2453 struct msm_dp_ctrl_private *ctrl;
2460 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2462 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock;
2464 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420)
2467 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
2468 ctrl->link->link_params.rate,
2469 ctrl->link->link_params.num_lanes, pixel_rate);
2471 drm_dbg_dp(ctrl->drm_dev,
2473 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on);
2475 if (!ctrl->link_clks_on) { /* link clk is off */
2476 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl);
2483 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000);
2489 if (ctrl->stream_clks_on) {
2490 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n");
2492 ret = clk_prepare_enable(ctrl->pixel_clk);
2497 ctrl->stream_clks_on = true;
2500 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl))
2501 msm_dp_ctrl_link_retrain(ctrl);
2504 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX);
2510 reinit_completion(&ctrl->video_comp);
2512 msm_dp_ctrl_configure_source_params(ctrl);
2514 msm_dp_ctrl_config_msa(ctrl,
2515 ctrl->link->link_params.rate,
2517 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420);
2519 msm_dp_panel_clear_dsc_dto(ctrl->panel);
2521 msm_dp_ctrl_setup_tr_unit(ctrl);
2523 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO);
2525 ret = msm_dp_ctrl_wait4video_ready(ctrl);
2529 mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl);
2530 drm_dbg_dp(ctrl->drm_dev,
2539 struct msm_dp_ctrl_private *ctrl;
2542 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2543 phy = ctrl->phy;
2545 msm_dp_panel_disable_vsc_sdp(ctrl->panel);
2548 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true);
2550 msm_dp_ctrl_mainlink_disable(ctrl);
2552 if (ctrl->stream_clks_on) {
2553 clk_disable_unprepare(ctrl->pixel_clk);
2554 ctrl->stream_clks_on = false;
2557 dev_pm_opp_set_rate(ctrl->dev, 0);
2558 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2566 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2572 struct msm_dp_ctrl_private *ctrl;
2575 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2576 phy = ctrl->phy;
2578 msm_dp_ctrl_mainlink_disable(ctrl);
2580 dev_pm_opp_set_rate(ctrl->dev, 0);
2581 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2594 struct msm_dp_ctrl_private *ctrl;
2597 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2598 phy = ctrl->phy;
2600 msm_dp_panel_disable_vsc_sdp(ctrl->panel);
2602 msm_dp_ctrl_mainlink_disable(ctrl);
2604 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl);
2606 if (ctrl->stream_clks_on) {
2607 clk_disable_unprepare(ctrl->pixel_clk);
2608 ctrl->stream_clks_on = false;
2611 dev_pm_opp_set_rate(ctrl->dev, 0);
2612 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl);
2615 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n",
2621 struct msm_dp_ctrl_private *ctrl;
2628 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2630 if (ctrl->panel->psr_cap.version) {
2631 isr = msm_dp_ctrl_get_psr_interrupt(ctrl);
2634 complete(&ctrl->psr_op_comp);
2637 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n");
2640 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n");
2643 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n");
2646 isr = msm_dp_ctrl_get_interrupt(ctrl);
2649 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n");
2650 complete(&ctrl->video_comp);
2655 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n");
2656 complete(&ctrl->idle_comp);
2661 isr = msm_dp_ctrl_get_aux_interrupt(ctrl);
2663 ret |= msm_dp_aux_isr(ctrl->aux, isr);
2680 struct msm_dp_ctrl_private *ctrl;
2684 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl);
2685 dev = ctrl->dev;
2687 ctrl->num_core_clks = ARRAY_SIZE(core_clks);
2688 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL);
2689 if (!ctrl->core_clks)
2692 for (i = 0; i < ctrl->num_core_clks; i++)
2693 ctrl->core_clks[i].id = core_clks[i];
2695 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks);
2699 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks);
2700 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL);
2701 if (!ctrl->link_clks)
2704 for (i = 0; i < ctrl->num_link_clks; i++)
2705 ctrl->link_clks[i].id = ctrl_clks[i];
2707 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks);
2711 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel");
2712 if (IS_ERR(ctrl->pixel_clk))
2713 return PTR_ERR(ctrl->pixel_clk);
2724 struct msm_dp_ctrl_private *ctrl;
2732 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2733 if (!ctrl) {
2750 init_completion(&ctrl->idle_comp);
2751 init_completion(&ctrl->psr_op_comp);
2752 init_completion(&ctrl->video_comp);
2755 ctrl->panel = panel;
2756 ctrl->aux = aux;
2757 ctrl->link = link;
2758 ctrl->dev = dev;
2759 ctrl->phy = phy;
2760 ctrl->ahb_base = ahb_base;
2761 ctrl->link_base = link_base;
2763 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl);
2769 return &ctrl->msm_dp_ctrl;