Lines Matching full:ctrl
145 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_ahb() argument
147 return readl_relaxed(ctrl->ahb_base + offset); in msm_dp_read_ahb()
150 static inline void msm_dp_write_ahb(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_ahb() argument
157 writel(data, ctrl->ahb_base + offset); in msm_dp_write_ahb()
160 static inline u32 msm_dp_read_link(struct msm_dp_ctrl_private *ctrl, u32 offset) in msm_dp_read_link() argument
162 return readl_relaxed(ctrl->link_base + offset); in msm_dp_read_link()
165 static inline void msm_dp_write_link(struct msm_dp_ctrl_private *ctrl, in msm_dp_write_link() argument
172 writel(data, ctrl->link_base + offset); in msm_dp_write_link()
199 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_reset() local
203 sw_reset = msm_dp_read_ahb(ctrl, REG_DP_SW_RESET); in msm_dp_ctrl_reset()
206 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); in msm_dp_ctrl_reset()
210 msm_dp_write_ahb(ctrl, REG_DP_SW_RESET, sw_reset); in msm_dp_ctrl_reset()
212 if (!ctrl->hw_revision) { in msm_dp_ctrl_reset()
213 ctrl->hw_revision = msm_dp_read_ahb(ctrl, REG_DP_HW_VERSION); in msm_dp_ctrl_reset()
214 ctrl->panel->hw_revision = ctrl->hw_revision; in msm_dp_ctrl_reset()
218 static u32 msm_dp_ctrl_get_aux_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_aux_interrupt() argument
222 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS); in msm_dp_ctrl_get_aux_interrupt()
226 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, in msm_dp_ctrl_get_aux_interrupt()
233 static u32 msm_dp_ctrl_get_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_interrupt() argument
237 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS2); in msm_dp_ctrl_get_interrupt()
241 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, in msm_dp_ctrl_get_interrupt()
249 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_enable_irq() local
252 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, in msm_dp_ctrl_enable_irq()
254 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, in msm_dp_ctrl_enable_irq()
260 struct msm_dp_ctrl_private *ctrl = in msm_dp_ctrl_disable_irq() local
263 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); in msm_dp_ctrl_disable_irq()
264 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); in msm_dp_ctrl_disable_irq()
267 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_get_psr_interrupt() argument
271 intr = msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS4); in msm_dp_ctrl_get_psr_interrupt()
274 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS4, intr_ack); in msm_dp_ctrl_get_psr_interrupt()
279 static void msm_dp_ctrl_config_psr_interrupt(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_config_psr_interrupt() argument
281 msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); in msm_dp_ctrl_config_psr_interrupt()
284 static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_mainlink_enable() argument
288 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_psr_mainlink_enable()
290 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); in msm_dp_ctrl_psr_mainlink_enable()
293 static void msm_dp_ctrl_psr_mainlink_disable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_mainlink_disable() argument
297 val = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_psr_mainlink_disable()
299 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, val); in msm_dp_ctrl_psr_mainlink_disable()
302 static void msm_dp_ctrl_mainlink_enable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_enable() argument
306 drm_dbg_dp(ctrl->drm_dev, "enable\n"); in msm_dp_ctrl_mainlink_enable()
308 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_mainlink_enable()
312 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
315 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
318 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
322 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_enable()
325 static void msm_dp_ctrl_mainlink_disable(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_disable() argument
329 drm_dbg_dp(ctrl->drm_dev, "disable\n"); in msm_dp_ctrl_mainlink_disable()
331 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_mainlink_disable()
333 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_ctrl_mainlink_disable()
336 static void msm_dp_setup_peripheral_flush(struct msm_dp_ctrl_private *ctrl) in msm_dp_setup_peripheral_flush() argument
340 mainlink_ctrl = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_setup_peripheral_flush()
342 if (ctrl->hw_revision >= DP_HW_VERSION_1_2) in msm_dp_setup_peripheral_flush()
347 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); in msm_dp_setup_peripheral_flush()
350 static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_mainlink_ready() argument
356 ret = readl_poll_timeout(ctrl->link_base + REG_DP_MAINLINK_READY, in msm_dp_ctrl_mainlink_ready()
369 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_push_idle() local
371 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_push_idle()
373 reinit_completion(&ctrl->idle_comp); in msm_dp_ctrl_push_idle()
374 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); in msm_dp_ctrl_push_idle()
376 if (!wait_for_completion_timeout(&ctrl->idle_comp, in msm_dp_ctrl_push_idle()
380 drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); in msm_dp_ctrl_push_idle()
383 static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_config_ctrl() argument
386 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_config_ctrl()
391 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_config_ctrl()
398 tbd = msm_dp_link_get_test_bits_depth(ctrl->link, in msm_dp_ctrl_config_ctrl()
399 ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_config_ctrl()
404 config |= ((ctrl->link->link_params.num_lanes - 1) in msm_dp_ctrl_config_ctrl()
416 if (ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_ctrl()
419 drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=0x%x\n", config); in msm_dp_ctrl_config_ctrl()
421 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); in msm_dp_ctrl_config_ctrl()
424 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_lane_mapping() argument
426 u32 *lane_map = ctrl->link->lane_map; in msm_dp_ctrl_lane_mapping()
434 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, in msm_dp_ctrl_lane_mapping()
438 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_configure_source_params() argument
442 msm_dp_ctrl_lane_mapping(ctrl); in msm_dp_ctrl_configure_source_params()
443 msm_dp_setup_peripheral_flush(ctrl); in msm_dp_ctrl_configure_source_params()
445 msm_dp_ctrl_config_ctrl(ctrl); in msm_dp_ctrl_configure_source_params()
447 test_bits_depth = msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->panel->msm_dp_mode.bpp); in msm_dp_ctrl_configure_source_params()
448 colorimetry_cfg = msm_dp_link_get_colorimetry_config(ctrl->link); in msm_dp_ctrl_configure_source_params()
450 misc_val = msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); in msm_dp_ctrl_configure_source_params()
459 drm_dbg_dp(ctrl->drm_dev, "misc settings = 0x%x\n", misc_val); in msm_dp_ctrl_configure_source_params()
460 msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); in msm_dp_ctrl_configure_source_params()
462 msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); in msm_dp_ctrl_configure_source_params()
897 static void _dp_ctrl_calc_tu(struct msm_dp_ctrl_private *ctrl, in _dp_ctrl_calc_tu() argument
982 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
1018 drm_dbg_dp(ctrl->drm_dev, in _dp_ctrl_calc_tu()
1213 drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n", in _dp_ctrl_calc_tu()
1215 drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n", in _dp_ctrl_calc_tu()
1217 drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n", in _dp_ctrl_calc_tu()
1219 drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n", in _dp_ctrl_calc_tu()
1221 drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n", in _dp_ctrl_calc_tu()
1223 drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n", in _dp_ctrl_calc_tu()
1225 drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n", in _dp_ctrl_calc_tu()
1231 static void msm_dp_ctrl_calc_tu_parameters(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_calc_tu_parameters() argument
1237 drm_mode = &ctrl->panel->msm_dp_mode.drm_mode; in msm_dp_ctrl_calc_tu_parameters()
1239 in.lclk = ctrl->link->link_params.rate / 1000; in msm_dp_ctrl_calc_tu_parameters()
1243 in.nlanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_calc_tu_parameters()
1244 in.bpp = ctrl->panel->msm_dp_mode.bpp; in msm_dp_ctrl_calc_tu_parameters()
1245 in.pixel_enc = ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in msm_dp_ctrl_calc_tu_parameters()
1252 _dp_ctrl_calc_tu(ctrl, &in, tu_table); in msm_dp_ctrl_calc_tu_parameters()
1255 static void msm_dp_ctrl_setup_tr_unit(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_setup_tr_unit() argument
1262 msm_dp_ctrl_calc_tu_parameters(ctrl, &tu_calc_table); in msm_dp_ctrl_setup_tr_unit()
1278 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY, valid_boundary); in msm_dp_ctrl_setup_tr_unit()
1279 msm_dp_write_link(ctrl, REG_DP_TU, msm_dp_tu); in msm_dp_ctrl_setup_tr_unit()
1280 msm_dp_write_link(ctrl, REG_DP_VALID_BOUNDARY_2, valid_boundary2); in msm_dp_ctrl_setup_tr_unit()
1283 static int msm_dp_ctrl_wait4video_ready(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_wait4video_ready() argument
1287 if (!wait_for_completion_timeout(&ctrl->video_comp, in msm_dp_ctrl_wait4video_ready()
1295 static int msm_dp_ctrl_set_vx_px(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_set_vx_px() argument
1298 union phy_configure_opts *phy_opts = &ctrl->phy_opts; in msm_dp_ctrl_set_vx_px()
1304 phy_configure(ctrl->phy, phy_opts); in msm_dp_ctrl_set_vx_px()
1310 static int msm_dp_ctrl_update_phy_vx_px(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_update_phy_vx_px() argument
1313 struct msm_dp_link *link = ctrl->link; in msm_dp_ctrl_update_phy_vx_px()
1321 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1324 ret = msm_dp_ctrl_set_vx_px(ctrl, in msm_dp_ctrl_update_phy_vx_px()
1331 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1338 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_update_phy_vx_px()
1346 lane_cnt = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_update_phy_vx_px()
1351 drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n", in msm_dp_ctrl_update_phy_vx_px()
1359 ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt); in msm_dp_ctrl_update_phy_vx_px()
1366 static bool msm_dp_ctrl_train_pattern_set(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_train_pattern_set() argument
1373 drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n", pattern); in msm_dp_ctrl_train_pattern_set()
1385 ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf); in msm_dp_ctrl_train_pattern_set()
1389 static int msm_dp_ctrl_set_pattern_state_bit(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_set_pattern_state_bit() argument
1396 drm_dbg_dp(ctrl->drm_dev, "hw: bit=%d train=%d\n", bit, state_bit); in msm_dp_ctrl_set_pattern_state_bit()
1397 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, bit); in msm_dp_ctrl_set_pattern_state_bit()
1402 ret = readx_poll_timeout(readl, ctrl->link_base + REG_DP_MAINLINK_READY, in msm_dp_ctrl_set_pattern_state_bit()
1413 static int msm_dp_ctrl_link_train_1(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_1() argument
1421 delay_us = drm_dp_read_clock_recovery_delay(ctrl->aux, in msm_dp_ctrl_link_train_1()
1422 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_1()
1424 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train_1()
1428 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, 1); in msm_dp_ctrl_link_train_1()
1431 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | in msm_dp_ctrl_link_train_1()
1434 msm_dp_link_reset_phy_params_vx_px(ctrl->link); in msm_dp_ctrl_link_train_1()
1435 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_1()
1440 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1444 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); in msm_dp_ctrl_link_train_1()
1449 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_1()
1453 if (ctrl->link->phy_params.v_level >= in msm_dp_ctrl_link_train_1()
1459 if (old_v_level != ctrl->link->phy_params.v_level) { in msm_dp_ctrl_link_train_1()
1461 old_v_level = ctrl->link->phy_params.v_level; in msm_dp_ctrl_link_train_1()
1464 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_1()
1465 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_1()
1474 static int msm_dp_ctrl_link_rate_down_shift(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_rate_down_shift() argument
1478 switch (ctrl->link->link_params.rate) { in msm_dp_ctrl_link_rate_down_shift()
1480 ctrl->link->link_params.rate = 540000; in msm_dp_ctrl_link_rate_down_shift()
1483 ctrl->link->link_params.rate = 270000; in msm_dp_ctrl_link_rate_down_shift()
1486 ctrl->link->link_params.rate = 162000; in msm_dp_ctrl_link_rate_down_shift()
1495 drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n", in msm_dp_ctrl_link_rate_down_shift()
1496 ctrl->link->link_params.rate); in msm_dp_ctrl_link_rate_down_shift()
1502 static int msm_dp_ctrl_link_lane_down_shift(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_lane_down_shift() argument
1505 if (ctrl->link->link_params.num_lanes == 1) in msm_dp_ctrl_link_lane_down_shift()
1508 ctrl->link->link_params.num_lanes /= 2; in msm_dp_ctrl_link_lane_down_shift()
1509 ctrl->link->link_params.rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_link_lane_down_shift()
1511 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1512 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_lane_down_shift()
1517 static void msm_dp_ctrl_clear_training_pattern(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_clear_training_pattern() argument
1522 msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE, dp_phy); in msm_dp_ctrl_clear_training_pattern()
1524 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, in msm_dp_ctrl_clear_training_pattern()
1525 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_clear_training_pattern()
1529 static int msm_dp_ctrl_link_train_2(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_2() argument
1539 delay_us = drm_dp_read_channel_eq_delay(ctrl->aux, in msm_dp_ctrl_link_train_2()
1540 ctrl->panel->dpcd, dp_phy, false); in msm_dp_ctrl_link_train_2()
1542 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train_2()
1546 if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1549 } else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { in msm_dp_ctrl_link_train_2()
1557 ret = msm_dp_ctrl_set_pattern_state_bit(ctrl, state_ctrl_bit); in msm_dp_ctrl_link_train_2()
1561 msm_dp_ctrl_train_pattern_set(ctrl, pattern, dp_phy); in msm_dp_ctrl_link_train_2()
1566 ret = drm_dp_dpcd_read_phy_link_status(ctrl->aux, dp_phy, link_status); in msm_dp_ctrl_link_train_2()
1571 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_link_train_2()
1575 msm_dp_link_adjust_levels(ctrl->link, link_status); in msm_dp_ctrl_link_train_2()
1576 ret = msm_dp_ctrl_update_phy_vx_px(ctrl, dp_phy); in msm_dp_ctrl_link_train_2()
1585 static int msm_dp_ctrl_link_train_1_2(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train_1_2() argument
1590 ret = msm_dp_ctrl_link_train_1(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train_1_2()
1595 drm_dbg_dp(ctrl->drm_dev, "link training #1 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1597 ret = msm_dp_ctrl_link_train_2(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train_1_2()
1602 drm_dbg_dp(ctrl->drm_dev, "link training #2 on phy %d successful\n", dp_phy); in msm_dp_ctrl_link_train_1_2()
1607 static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_link_train() argument
1612 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_link_train()
1617 msm_dp_ctrl_config_ctrl(ctrl); in msm_dp_ctrl_link_train()
1619 link_info.num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_link_train()
1620 link_info.rate = ctrl->link->link_params.rate; in msm_dp_ctrl_link_train()
1623 msm_dp_aux_link_configure(ctrl->aux, &link_info); in msm_dp_ctrl_link_train()
1629 drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2); in msm_dp_ctrl_link_train()
1633 drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET, in msm_dp_ctrl_link_train()
1637 for (i = ctrl->link->lttpr_count - 1; i >= 0; i--) { in msm_dp_ctrl_link_train()
1640 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, dp_phy); in msm_dp_ctrl_link_train()
1641 msm_dp_ctrl_clear_training_pattern(ctrl, dp_phy); in msm_dp_ctrl_link_train()
1652 ret = msm_dp_ctrl_link_train_1_2(ctrl, training_step, DP_PHY_DPRX); in msm_dp_ctrl_link_train()
1659 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_link_train()
1664 static int msm_dp_ctrl_setup_main_link(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_setup_main_link() argument
1669 msm_dp_ctrl_mainlink_enable(ctrl); in msm_dp_ctrl_setup_main_link()
1671 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_setup_main_link()
1680 ret = msm_dp_ctrl_link_train(ctrl, training_step); in msm_dp_ctrl_setup_main_link()
1687 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_core_clk_enable() local
1690 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_core_clk_enable()
1692 if (ctrl->core_clks_on) { in msm_dp_ctrl_core_clk_enable()
1693 drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); in msm_dp_ctrl_core_clk_enable()
1697 ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_enable()
1701 ctrl->core_clks_on = true; in msm_dp_ctrl_core_clk_enable()
1703 drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); in msm_dp_ctrl_core_clk_enable()
1704 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_enable()
1705 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_core_clk_enable()
1706 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_core_clk_enable()
1707 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_core_clk_enable()
1714 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_core_clk_disable() local
1716 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_core_clk_disable()
1718 clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_core_clk_disable()
1720 ctrl->core_clks_on = false; in msm_dp_ctrl_core_clk_disable()
1722 drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); in msm_dp_ctrl_core_clk_disable()
1723 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_core_clk_disable()
1724 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_core_clk_disable()
1725 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_core_clk_disable()
1726 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_core_clk_disable()
1731 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_link_clk_enable() local
1734 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_link_clk_enable()
1736 if (ctrl->link_clks_on) { in msm_dp_ctrl_link_clk_enable()
1737 drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); in msm_dp_ctrl_link_clk_enable()
1741 if (!ctrl->core_clks_on) { in msm_dp_ctrl_link_clk_enable()
1742 drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); in msm_dp_ctrl_link_clk_enable()
1747 ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_enable()
1751 ctrl->link_clks_on = true; in msm_dp_ctrl_link_clk_enable()
1753 drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); in msm_dp_ctrl_link_clk_enable()
1754 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_enable()
1755 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_link_clk_enable()
1756 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_link_clk_enable()
1757 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_link_clk_enable()
1764 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_link_clk_disable() local
1766 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_link_clk_disable()
1768 clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_link_clk_disable()
1770 ctrl->link_clks_on = false; in msm_dp_ctrl_link_clk_disable()
1772 drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); in msm_dp_ctrl_link_clk_disable()
1773 drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", in msm_dp_ctrl_link_clk_disable()
1774 str_on_off(ctrl->stream_clks_on), in msm_dp_ctrl_link_clk_disable()
1775 str_on_off(ctrl->link_clks_on), in msm_dp_ctrl_link_clk_disable()
1776 str_on_off(ctrl->core_clks_on)); in msm_dp_ctrl_link_clk_disable()
1779 static int msm_dp_ctrl_enable_mainlink_clocks(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_enable_mainlink_clocks() argument
1782 struct phy *phy = ctrl->phy; in msm_dp_ctrl_enable_mainlink_clocks()
1783 const u8 *dpcd = ctrl->panel->dpcd; in msm_dp_ctrl_enable_mainlink_clocks()
1785 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_enable_mainlink_clocks()
1786 ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; in msm_dp_ctrl_enable_mainlink_clocks()
1787 ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); in msm_dp_ctrl_enable_mainlink_clocks()
1789 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_enable_mainlink_clocks()
1792 dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); in msm_dp_ctrl_enable_mainlink_clocks()
1793 ret = msm_dp_ctrl_link_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_enable_mainlink_clocks()
1797 drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate); in msm_dp_ctrl_enable_mainlink_clocks()
1802 static void msm_dp_ctrl_enable_sdp(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_enable_sdp() argument
1805 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, UPDATE_SDP); in msm_dp_ctrl_enable_sdp()
1806 msm_dp_write_link(ctrl, MMSS_DP_SDP_CFG3, 0x0); in msm_dp_ctrl_enable_sdp()
1809 static void msm_dp_ctrl_psr_enter(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_enter() argument
1813 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); in msm_dp_ctrl_psr_enter()
1818 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_psr_enter()
1819 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); in msm_dp_ctrl_psr_enter()
1822 static void msm_dp_ctrl_psr_exit(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_psr_exit() argument
1826 cmd = msm_dp_read_link(ctrl, REG_PSR_CMD); in msm_dp_ctrl_psr_exit()
1831 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_psr_exit()
1832 msm_dp_write_link(ctrl, REG_PSR_CMD, cmd); in msm_dp_ctrl_psr_exit()
1837 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, in msm_dp_ctrl_config_psr() local
1841 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_config_psr()
1845 cfg = msm_dp_read_link(ctrl, REG_PSR_CONFIG); in msm_dp_ctrl_config_psr()
1847 msm_dp_write_link(ctrl, REG_PSR_CONFIG, cfg); in msm_dp_ctrl_config_psr()
1849 msm_dp_ctrl_config_psr_interrupt(ctrl); in msm_dp_ctrl_config_psr()
1850 msm_dp_ctrl_enable_sdp(ctrl); in msm_dp_ctrl_config_psr()
1853 drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1); in msm_dp_ctrl_config_psr()
1858 struct msm_dp_ctrl_private *ctrl = container_of(msm_dp_ctrl, in msm_dp_ctrl_set_psr() local
1861 if (!ctrl->panel->psr_cap.version) in msm_dp_ctrl_set_psr()
1875 reinit_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_set_psr()
1876 msm_dp_ctrl_psr_enter(ctrl); in msm_dp_ctrl_set_psr()
1878 if (!wait_for_completion_timeout(&ctrl->psr_op_comp, in msm_dp_ctrl_set_psr()
1881 msm_dp_ctrl_psr_exit(ctrl); in msm_dp_ctrl_set_psr()
1886 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_set_psr()
1888 msm_dp_ctrl_psr_mainlink_disable(ctrl); in msm_dp_ctrl_set_psr()
1890 msm_dp_ctrl_psr_mainlink_enable(ctrl); in msm_dp_ctrl_set_psr()
1892 msm_dp_ctrl_psr_exit(ctrl); in msm_dp_ctrl_set_psr()
1893 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_set_psr()
1894 msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_set_psr()
1895 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); in msm_dp_ctrl_set_psr()
1899 static void msm_dp_ctrl_phy_reset(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_phy_reset() argument
1901 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, in msm_dp_ctrl_phy_reset()
1904 msm_dp_write_ahb(ctrl, REG_DP_PHY_CTRL, 0x0); in msm_dp_ctrl_phy_reset()
1909 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_phy_init() local
1912 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_phy_init()
1913 phy = ctrl->phy; in msm_dp_ctrl_phy_init()
1915 msm_dp_ctrl_phy_reset(ctrl); in msm_dp_ctrl_phy_init()
1918 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_init()
1924 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_phy_exit() local
1927 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_phy_exit()
1928 phy = ctrl->phy; in msm_dp_ctrl_phy_exit()
1930 msm_dp_ctrl_phy_reset(ctrl); in msm_dp_ctrl_phy_exit()
1932 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_phy_exit()
1936 static int msm_dp_ctrl_reinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_reinitialize_mainlink() argument
1938 struct phy *phy = ctrl->phy; in msm_dp_ctrl_reinitialize_mainlink()
1941 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1942 ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_reinitialize_mainlink()
1943 phy_configure(phy, &ctrl->phy_opts); in msm_dp_ctrl_reinitialize_mainlink()
1949 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_reinitialize_mainlink()
1951 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1957 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_reinitialize_mainlink()
1966 static int msm_dp_ctrl_deinitialize_mainlink(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_deinitialize_mainlink() argument
1970 phy = ctrl->phy; in msm_dp_ctrl_deinitialize_mainlink()
1972 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1974 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1976 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_deinitialize_mainlink()
1977 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_deinitialize_mainlink()
1985 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_deinitialize_mainlink()
1990 static int msm_dp_ctrl_link_maintenance(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_maintenance() argument
1995 msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_link_maintenance()
1997 ctrl->link->phy_params.p_level = 0; in msm_dp_ctrl_link_maintenance()
1998 ctrl->link->phy_params.v_level = 0; in msm_dp_ctrl_link_maintenance()
2000 ret = msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_link_maintenance()
2004 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_link_maintenance()
2006 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_link_maintenance()
2008 ret = msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_link_maintenance()
2015 static void msm_dp_ctrl_send_phy_pattern(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_send_phy_pattern() argument
2021 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0x0); in msm_dp_ctrl_send_phy_pattern()
2023 drm_dbg_dp(ctrl->drm_dev, "pattern: %#x\n", pattern); in msm_dp_ctrl_send_phy_pattern()
2026 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2032 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2035 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2037 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, in msm_dp_ctrl_send_phy_pattern()
2039 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2044 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2049 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2052 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0, in msm_dp_ctrl_send_phy_pattern()
2055 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1, in msm_dp_ctrl_send_phy_pattern()
2058 msm_dp_write_link(ctrl, REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2, in msm_dp_ctrl_send_phy_pattern()
2063 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_send_phy_pattern()
2065 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); in msm_dp_ctrl_send_phy_pattern()
2068 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2071 msm_dp_write_link(ctrl, REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET, in msm_dp_ctrl_send_phy_pattern()
2073 msm_dp_write_link(ctrl, REG_DP_MAINLINK_LEVELS, in msm_dp_ctrl_send_phy_pattern()
2075 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2077 value = msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); in msm_dp_ctrl_send_phy_pattern()
2079 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, value); in msm_dp_ctrl_send_phy_pattern()
2083 msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, in msm_dp_ctrl_send_phy_pattern()
2085 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, in msm_dp_ctrl_send_phy_pattern()
2090 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_send_phy_pattern()
2096 static bool msm_dp_ctrl_send_phy_test_pattern(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_send_phy_test_pattern() argument
2100 u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; in msm_dp_ctrl_send_phy_test_pattern()
2102 drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
2104 if (msm_dp_ctrl_set_vx_px(ctrl, in msm_dp_ctrl_send_phy_test_pattern()
2105 ctrl->link->phy_params.v_level, in msm_dp_ctrl_send_phy_test_pattern()
2106 ctrl->link->phy_params.p_level)) { in msm_dp_ctrl_send_phy_test_pattern()
2110 msm_dp_ctrl_send_phy_pattern(ctrl, pattern_requested); in msm_dp_ctrl_send_phy_test_pattern()
2111 msm_dp_ctrl_update_phy_vx_px(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_send_phy_test_pattern()
2112 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_send_phy_test_pattern()
2114 pattern_sent = msm_dp_read_link(ctrl, REG_DP_MAINLINK_READY); in msm_dp_ctrl_send_phy_test_pattern()
2143 drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n", in msm_dp_ctrl_send_phy_test_pattern()
2148 static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_process_phy_test_request() argument
2153 if (!ctrl->link->phy_params.phy_test_pattern_sel) { in msm_dp_ctrl_process_phy_test_request()
2154 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_process_phy_test_request()
2164 msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
2166 ret = msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_process_phy_test_request()
2172 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_process_phy_test_request()
2173 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_process_phy_test_request()
2179 if (ctrl->stream_clks_on) { in msm_dp_ctrl_process_phy_test_request()
2180 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_process_phy_test_request()
2182 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_process_phy_test_request()
2187 ctrl->stream_clks_on = true; in msm_dp_ctrl_process_phy_test_request()
2190 msm_dp_ctrl_send_phy_test_pattern(ctrl); in msm_dp_ctrl_process_phy_test_request()
2197 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_handle_sink_request() local
2205 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_handle_sink_request()
2206 sink_request = ctrl->link->sink_request; in msm_dp_ctrl_handle_sink_request()
2209 drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n"); in msm_dp_ctrl_handle_sink_request()
2210 if (msm_dp_ctrl_process_phy_test_request(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2217 if (msm_dp_ctrl_link_maintenance(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2224 msm_dp_link_send_test_response(ctrl->link); in msm_dp_ctrl_handle_sink_request()
2225 if (msm_dp_ctrl_link_maintenance(ctrl)) { in msm_dp_ctrl_handle_sink_request()
2251 static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_channel_eq_ok() argument
2254 int num_lanes = ctrl->link->link_params.num_lanes; in msm_dp_ctrl_channel_eq_ok()
2256 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_channel_eq_ok()
2264 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_on_link() local
2275 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_on_link()
2277 rate = ctrl->panel->link_info.rate; in msm_dp_ctrl_on_link()
2278 pixel_rate = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_link()
2280 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_on_link()
2282 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { in msm_dp_ctrl_on_link()
2283 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_link()
2288 ctrl->link->link_params.rate = rate; in msm_dp_ctrl_on_link()
2289 ctrl->link->link_params.num_lanes = in msm_dp_ctrl_on_link()
2290 ctrl->panel->link_info.num_lanes; in msm_dp_ctrl_on_link()
2291 if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_link()
2295 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_link()
2296 ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, in msm_dp_ctrl_on_link()
2299 rc = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_on_link()
2305 rc = msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_on_link()
2311 if (!msm_dp_aux_is_link_connected(ctrl->aux)) in msm_dp_ctrl_on_link()
2314 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_on_link()
2316 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); in msm_dp_ctrl_on_link()
2319 ctrl->link->link_params.num_lanes)) { in msm_dp_ctrl_on_link()
2324 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); in msm_dp_ctrl_on_link()
2336 if (!msm_dp_aux_is_link_connected(ctrl->aux)) in msm_dp_ctrl_on_link()
2339 drm_dp_dpcd_read_link_status(ctrl->aux, link_status); in msm_dp_ctrl_on_link()
2342 ctrl->link->link_params.num_lanes)) in msm_dp_ctrl_on_link()
2343 rc = msm_dp_ctrl_link_rate_down_shift(ctrl); in msm_dp_ctrl_on_link()
2345 rc = msm_dp_ctrl_link_lane_down_shift(ctrl); in msm_dp_ctrl_on_link()
2353 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_link()
2356 rc = msm_dp_ctrl_reinitialize_mainlink(ctrl); in msm_dp_ctrl_on_link()
2363 if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) in msm_dp_ctrl_on_link()
2377 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_link()
2379 msm_dp_ctrl_deinitialize_mainlink(ctrl); in msm_dp_ctrl_on_link()
2386 static int msm_dp_ctrl_link_retrain(struct msm_dp_ctrl_private *ctrl) in msm_dp_ctrl_link_retrain() argument
2390 return msm_dp_ctrl_setup_main_link(ctrl, &training_step); in msm_dp_ctrl_link_retrain()
2393 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, in msm_dp_ctrl_config_msa() argument
2444 drm_dbg_dp(ctrl->drm_dev, "mvid=0x%x, nvid=0x%x\n", mvid, nvid); in msm_dp_ctrl_config_msa()
2445 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); in msm_dp_ctrl_config_msa()
2446 msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); in msm_dp_ctrl_config_msa()
2453 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_on_stream() local
2460 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_on_stream()
2462 pixel_rate = pixel_rate_orig = ctrl->panel->msm_dp_mode.drm_mode.clock; in msm_dp_ctrl_on_stream()
2464 if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) in msm_dp_ctrl_on_stream()
2467 drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", in msm_dp_ctrl_on_stream()
2468 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
2469 ctrl->link->link_params.num_lanes, pixel_rate); in msm_dp_ctrl_on_stream()
2471 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
2473 ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); in msm_dp_ctrl_on_stream()
2475 if (!ctrl->link_clks_on) { /* link clk is off */ in msm_dp_ctrl_on_stream()
2476 ret = msm_dp_ctrl_enable_mainlink_clocks(ctrl); in msm_dp_ctrl_on_stream()
2483 ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); in msm_dp_ctrl_on_stream()
2489 if (ctrl->stream_clks_on) { in msm_dp_ctrl_on_stream()
2490 drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); in msm_dp_ctrl_on_stream()
2492 ret = clk_prepare_enable(ctrl->pixel_clk); in msm_dp_ctrl_on_stream()
2497 ctrl->stream_clks_on = true; in msm_dp_ctrl_on_stream()
2500 if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) in msm_dp_ctrl_on_stream()
2501 msm_dp_ctrl_link_retrain(ctrl); in msm_dp_ctrl_on_stream()
2504 msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); in msm_dp_ctrl_on_stream()
2510 reinit_completion(&ctrl->video_comp); in msm_dp_ctrl_on_stream()
2512 msm_dp_ctrl_configure_source_params(ctrl); in msm_dp_ctrl_on_stream()
2514 msm_dp_ctrl_config_msa(ctrl, in msm_dp_ctrl_on_stream()
2515 ctrl->link->link_params.rate, in msm_dp_ctrl_on_stream()
2517 ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); in msm_dp_ctrl_on_stream()
2519 msm_dp_panel_clear_dsc_dto(ctrl->panel); in msm_dp_ctrl_on_stream()
2521 msm_dp_ctrl_setup_tr_unit(ctrl); in msm_dp_ctrl_on_stream()
2523 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); in msm_dp_ctrl_on_stream()
2525 ret = msm_dp_ctrl_wait4video_ready(ctrl); in msm_dp_ctrl_on_stream()
2529 mainlink_ready = msm_dp_ctrl_mainlink_ready(ctrl); in msm_dp_ctrl_on_stream()
2530 drm_dbg_dp(ctrl->drm_dev, in msm_dp_ctrl_on_stream()
2539 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off_link_stream() local
2542 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off_link_stream()
2543 phy = ctrl->phy; in msm_dp_ctrl_off_link_stream()
2545 msm_dp_panel_disable_vsc_sdp(ctrl->panel); in msm_dp_ctrl_off_link_stream()
2548 msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); in msm_dp_ctrl_off_link_stream()
2550 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off_link_stream()
2552 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off_link_stream()
2553 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off_link_stream()
2554 ctrl->stream_clks_on = false; in msm_dp_ctrl_off_link_stream()
2557 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link_stream()
2558 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link_stream()
2566 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off_link_stream()
2572 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off_link() local
2575 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off_link()
2576 phy = ctrl->phy; in msm_dp_ctrl_off_link()
2578 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off_link()
2580 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off_link()
2581 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off_link()
2594 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_off() local
2597 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_off()
2598 phy = ctrl->phy; in msm_dp_ctrl_off()
2600 msm_dp_panel_disable_vsc_sdp(ctrl->panel); in msm_dp_ctrl_off()
2602 msm_dp_ctrl_mainlink_disable(ctrl); in msm_dp_ctrl_off()
2604 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off()
2606 if (ctrl->stream_clks_on) { in msm_dp_ctrl_off()
2607 clk_disable_unprepare(ctrl->pixel_clk); in msm_dp_ctrl_off()
2608 ctrl->stream_clks_on = false; in msm_dp_ctrl_off()
2611 dev_pm_opp_set_rate(ctrl->dev, 0); in msm_dp_ctrl_off()
2612 msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_off()
2615 drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", in msm_dp_ctrl_off()
2621 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_isr() local
2628 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_isr()
2630 if (ctrl->panel->psr_cap.version) { in msm_dp_ctrl_isr()
2631 isr = msm_dp_ctrl_get_psr_interrupt(ctrl); in msm_dp_ctrl_isr()
2634 complete(&ctrl->psr_op_comp); in msm_dp_ctrl_isr()
2637 drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n"); in msm_dp_ctrl_isr()
2640 drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n"); in msm_dp_ctrl_isr()
2643 drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n"); in msm_dp_ctrl_isr()
2646 isr = msm_dp_ctrl_get_interrupt(ctrl); in msm_dp_ctrl_isr()
2649 drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n"); in msm_dp_ctrl_isr()
2650 complete(&ctrl->video_comp); in msm_dp_ctrl_isr()
2655 drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n"); in msm_dp_ctrl_isr()
2656 complete(&ctrl->idle_comp); in msm_dp_ctrl_isr()
2661 isr = msm_dp_ctrl_get_aux_interrupt(ctrl); in msm_dp_ctrl_isr()
2663 ret |= msm_dp_aux_isr(ctrl->aux, isr); in msm_dp_ctrl_isr()
2680 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_clk_init() local
2684 ctrl = container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctrl); in msm_dp_ctrl_clk_init()
2685 dev = ctrl->dev; in msm_dp_ctrl_clk_init()
2687 ctrl->num_core_clks = ARRAY_SIZE(core_clks); in msm_dp_ctrl_clk_init()
2688 ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2689 if (!ctrl->core_clks) in msm_dp_ctrl_clk_init()
2692 for (i = 0; i < ctrl->num_core_clks; i++) in msm_dp_ctrl_clk_init()
2693 ctrl->core_clks[i].id = core_clks[i]; in msm_dp_ctrl_clk_init()
2695 rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); in msm_dp_ctrl_clk_init()
2699 ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); in msm_dp_ctrl_clk_init()
2700 ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); in msm_dp_ctrl_clk_init()
2701 if (!ctrl->link_clks) in msm_dp_ctrl_clk_init()
2704 for (i = 0; i < ctrl->num_link_clks; i++) in msm_dp_ctrl_clk_init()
2705 ctrl->link_clks[i].id = ctrl_clks[i]; in msm_dp_ctrl_clk_init()
2707 rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); in msm_dp_ctrl_clk_init()
2711 ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); in msm_dp_ctrl_clk_init()
2712 if (IS_ERR(ctrl->pixel_clk)) in msm_dp_ctrl_clk_init()
2713 return PTR_ERR(ctrl->pixel_clk); in msm_dp_ctrl_clk_init()
2724 struct msm_dp_ctrl_private *ctrl; in msm_dp_ctrl_get() local
2732 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in msm_dp_ctrl_get()
2733 if (!ctrl) { in msm_dp_ctrl_get()
2750 init_completion(&ctrl->idle_comp); in msm_dp_ctrl_get()
2751 init_completion(&ctrl->psr_op_comp); in msm_dp_ctrl_get()
2752 init_completion(&ctrl->video_comp); in msm_dp_ctrl_get()
2755 ctrl->panel = panel; in msm_dp_ctrl_get()
2756 ctrl->aux = aux; in msm_dp_ctrl_get()
2757 ctrl->link = link; in msm_dp_ctrl_get()
2758 ctrl->dev = dev; in msm_dp_ctrl_get()
2759 ctrl->phy = phy; in msm_dp_ctrl_get()
2760 ctrl->ahb_base = ahb_base; in msm_dp_ctrl_get()
2761 ctrl->link_base = link_base; in msm_dp_ctrl_get()
2763 ret = msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); in msm_dp_ctrl_get()
2769 return &ctrl->msm_dp_ctrl; in msm_dp_ctrl_get()