Lines Matching defs:pdpu
201 struct dpu_plane *pdpu;
213 pdpu = to_dpu_plane(plane);
214 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
238 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
257 struct dpu_plane *pdpu = to_dpu_plane(plane);
261 if (!pdpu->is_rt_pipe) {
273 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
274 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage];
275 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage];
279 pdpu->is_rt_pipe)
282 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
283 pdpu->pipe - SSPP_VIG0,
285 pdpu->is_rt_pipe);
289 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
291 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
292 pdpu->pipe - SSPP_VIG0,
294 pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
296 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
302 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
303 pdpu->pipe - SSPP_VIG0,
322 struct dpu_plane *pdpu = to_dpu_plane(plane);
324 if (!pdpu->is_rt_pipe)
327 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
328 pdpu->pipe - SSPP_VIG0,
330 pdpu->is_rt_pipe);
365 struct dpu_plane *pdpu = to_dpu_plane(plane);
375 ot_params.is_wfd = !pdpu->is_rt_pipe;
399 struct dpu_plane *pdpu = to_dpu_plane(plane);
408 qos_params.is_rt = pdpu->is_rt_pipe;
410 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n",
611 * @pdpu: Pointer to DPU plane object
615 static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
619 const struct drm_plane *plane = &pdpu->base;
624 DPU_DEBUG_PLANE(pdpu, "\n");
648 struct dpu_plane *pdpu = to_dpu_plane(plane);
655 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
676 struct dpu_plane *pdpu = to_dpu_plane(plane);
684 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
689 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
707 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n",
722 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
729 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
764 DPU_DEBUG_PLANE(pdpu,
772 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
783 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
791 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
797 ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt);
804 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n");
819 struct dpu_plane *pdpu = to_dpu_plane(plane);
820 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
836 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
843 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
845 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
860 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n",
867 DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret);
875 max_linewidth = pdpu->catalog->caps->max_linewidth;
884 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
959 struct dpu_plane *pdpu = to_dpu_plane(plane);
967 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg,
974 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg,
1083 struct dpu_plane *pdpu = to_dpu_plane(plane);
1097 pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
1113 DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT
1285 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
1288 msm_framebuffer_format(pdpu->base.state->fb);
1298 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
1313 struct dpu_plane *pdpu;
1321 pdpu = to_dpu_plane(plane);
1328 if (pdpu->is_error)
1330 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
1331 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
1333 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1335 dpu_plane_flush_csc(pdpu, &pstate->pipe);
1336 dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
1351 struct dpu_plane *pdpu;
1356 pdpu = to_dpu_plane(plane);
1357 pdpu->is_error = error;
1368 struct dpu_plane *pdpu = to_dpu_plane(plane);
1378 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1414 const struct dpu_perf_cfg *perf = pdpu->catalog->perf;
1434 struct dpu_plane *pdpu = to_dpu_plane(plane);
1450 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
1451 pdpu->is_rt_pipe = is_rt_pipe;
1455 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1473 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1479 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1508 struct dpu_plane *pdpu = to_dpu_plane(plane);
1512 pdpu->is_error = false;
1514 DPU_DEBUG_PLANE(pdpu, "\n");
1533 struct dpu_plane *pdpu;
1546 pdpu = to_dpu_plane(plane);
1549 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1553 DPU_DEBUG_PLANE(pdpu, "\n");
1624 struct dpu_plane *pdpu;
1632 pdpu = to_dpu_plane(plane);
1633 DPU_DEBUG_PLANE(pdpu, "\n");
1643 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1653 struct dpu_plane *pdpu = to_dpu_plane(plane);
1657 if (!pdpu->is_rt_pipe)
1719 struct dpu_plane *pdpu;
1725 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base,
1729 if (IS_ERR(pdpu))
1730 return ERR_CAST(pdpu);
1733 plane = &pdpu->base;
1734 pdpu->pipe = pipe;
1736 pdpu->catalog = kms->catalog;