29 static inline void set_preempt_state(struct a6xx_gpu *gpu,  in set_preempt_state()  argument
38 	atomic_set(&gpu->preempt_state, new);  in set_preempt_state()
44 static inline void update_wptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in update_wptr()  argument
54 		gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);  in update_wptr()
63 static struct msm_ringbuffer *get_next_ring(struct msm_gpu *gpu)  in get_next_ring()  argument
65 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in get_next_ring()
71 	for (i = 0; i < gpu->nr_rings; i++) {  in get_next_ring()
73 		struct msm_ringbuffer *ring = gpu->rb[i];  in get_next_ring()
76 		empty = (get_wptr(ring) == gpu->funcs->get_rptr(gpu, ring));  in get_next_ring()
92 	struct msm_gpu *gpu = &a6xx_gpu->base.base;  in a6xx_preempt_timer()  local
93 	struct drm_device *dev = gpu->dev;  in a6xx_preempt_timer()
98 	dev_err(dev->dev, "%s: preemption timed out\n", gpu->name);  in a6xx_preempt_timer()
99 	kthread_queue_work(gpu->worker, &gpu->recover_work);  in a6xx_preempt_timer()
139 void a6xx_preempt_irq(struct msm_gpu *gpu)  in a6xx_preempt_irq()  argument
142 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_irq()
144 	struct drm_device *dev = gpu->dev;  in a6xx_preempt_irq()
159 	status = gpu_read(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL);  in a6xx_preempt_irq()
161 		DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_preempt_irq()
165 			gpu->name);  in a6xx_preempt_irq()
166 		kthread_queue_work(gpu->worker, &gpu->recover_work);  in a6xx_preempt_irq()
175 	update_wptr(gpu, a6xx_gpu->cur_ring);  in a6xx_preempt_irq()
185 	a6xx_preempt_trigger(gpu);  in a6xx_preempt_irq()
188 void a6xx_preempt_hw_init(struct msm_gpu *gpu)  in a6xx_preempt_hw_init()  argument
190 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_hw_init()
195 	if (gpu->nr_rings == 1)  in a6xx_preempt_hw_init()
198 	for (i = 0; i < gpu->nr_rings; i++) {  in a6xx_preempt_hw_init()
203 		record_ptr->rptr_addr = shadowptr(a6xx_gpu, gpu->rb[i]);  in a6xx_preempt_hw_init()
206 		record_ptr->rbase = gpu->rb[i]->iova;  in a6xx_preempt_hw_init()
210 	gpu_write64(gpu, REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO, 0);  in a6xx_preempt_hw_init()
213 	gpu_write(gpu, REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0x1);  in a6xx_preempt_hw_init()
221 	a6xx_gpu->cur_ring = gpu->rb[0];  in a6xx_preempt_hw_init()
224 void a6xx_preempt_trigger(struct msm_gpu *gpu)  in a6xx_preempt_trigger()  argument
226 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_trigger()
233 	if (gpu->nr_rings == 1)  in a6xx_preempt_trigger()
263 	ring = get_next_ring(gpu);  in a6xx_preempt_trigger()
271 		update_wptr(gpu, a6xx_gpu->cur_ring);  in a6xx_preempt_trigger()
292 	 * The GPU will write the wptr we set above when we preempt. Reset  in a6xx_preempt_trigger()
305 	gpu_write64(gpu,  in a6xx_preempt_trigger()
309 	gpu_write64(gpu,  in a6xx_preempt_trigger()
331 	gpu_write(gpu, REG_A6XX_CP_CONTEXT_SWITCH_CNTL, cntl);  in a6xx_preempt_trigger()
338 	struct msm_gpu *gpu = &adreno_gpu->base;  in preempt_init_ring()  local
345 	ptr = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
347 		MSM_BO_WC | MSM_BO_MAP_PRIV, gpu->vm, &bo, &iova);  in preempt_init_ring()
362 	ptr = msm_gem_kernel_new(gpu->dev,  in preempt_init_ring()
365 		gpu->vm, &bo, &iova);  in preempt_init_ring()
380 	msm_iommu_pagetable_params(to_msm_vm(gpu->vm)->mmu, &ttbr, &asid);  in preempt_init_ring()
401 void a6xx_preempt_fini(struct msm_gpu *gpu)  in a6xx_preempt_fini()  argument
403 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_fini()
407 	for (i = 0; i < gpu->nr_rings; i++)  in a6xx_preempt_fini()
408 		msm_gem_kernel_put(a6xx_gpu->preempt_bo[i], gpu->vm);  in a6xx_preempt_fini()
411 void a6xx_preempt_init(struct msm_gpu *gpu)  in a6xx_preempt_init()  argument
413 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a6xx_preempt_init()
418 	if (gpu->nr_rings <= 1)  in a6xx_preempt_init()
421 	for (i = 0; i < gpu->nr_rings; i++) {  in a6xx_preempt_init()
422 		if (preempt_init_ring(a6xx_gpu, gpu->rb[i]))  in a6xx_preempt_init()
431 	a6xx_gpu->preempt_postamble_ptr  = msm_gem_kernel_new(gpu->dev,  in a6xx_preempt_init()
434 			gpu->vm, &a6xx_gpu->preempt_postamble_bo,  in a6xx_preempt_init()
450 	a6xx_preempt_fini(gpu);  in a6xx_preempt_init()
451 	gpu->nr_rings = 1;  in a6xx_preempt_init()
453 	DRM_DEV_ERROR(&gpu->pdev->dev,  in a6xx_preempt_init()