Lines Matching +full:fixed +full:- +full:header
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
8 #include <soc/qcom/cmd-db.h>
32 struct a6xx_hfi_queue_header *header = queue->header; in a6xx_hfi_queue_read() local
33 u32 i, hdr, index = header->read_index; in a6xx_hfi_queue_read()
35 if (header->read_index == header->write_index) { in a6xx_hfi_queue_read()
36 header->rx_request = 1; in a6xx_hfi_queue_read()
40 hdr = queue->data[index]; in a6xx_hfi_queue_read()
42 queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index; in a6xx_hfi_queue_read()
47 * then we can also assume that if the header size is unexpectedly large in a6xx_hfi_queue_read()
56 data[i] = queue->data[index]; in a6xx_hfi_queue_read()
57 index = (index + 1) % header->size; in a6xx_hfi_queue_read()
60 if (!gmu->legacy) in a6xx_hfi_queue_read()
61 index = ALIGN(index, 4) % header->size; in a6xx_hfi_queue_read()
63 header->read_index = index; in a6xx_hfi_queue_read()
70 struct a6xx_hfi_queue_header *header = queue->header; in a6xx_hfi_queue_write() local
71 u32 i, space, index = header->write_index; in a6xx_hfi_queue_write()
73 spin_lock(&queue->lock); in a6xx_hfi_queue_write()
75 space = CIRC_SPACE(header->write_index, header->read_index, in a6xx_hfi_queue_write()
76 header->size); in a6xx_hfi_queue_write()
78 header->dropped++; in a6xx_hfi_queue_write()
79 spin_unlock(&queue->lock); in a6xx_hfi_queue_write()
80 return -ENOSPC; in a6xx_hfi_queue_write()
83 queue->history[(queue->history_idx++) % HFI_HISTORY_SZ] = index; in a6xx_hfi_queue_write()
86 queue->data[index] = data[i]; in a6xx_hfi_queue_write()
87 index = (index + 1) % header->size; in a6xx_hfi_queue_write()
91 if (!gmu->legacy) { in a6xx_hfi_queue_write()
92 for (; index % 4; index = (index + 1) % header->size) in a6xx_hfi_queue_write()
93 queue->data[index] = 0xfafafafa; in a6xx_hfi_queue_write()
96 header->write_index = index; in a6xx_hfi_queue_write()
97 spin_unlock(&queue->lock); in a6xx_hfi_queue_write()
106 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
115 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
118 return -ETIMEDOUT; in a6xx_hfi_wait_for_ack()
134 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
137 return -ENOENT; in a6xx_hfi_wait_for_ack()
140 if (HFI_HEADER_ID(resp.header) == HFI_F2H_MSG_ERROR) { in a6xx_hfi_wait_for_ack()
144 DRM_DEV_ERROR(gmu->dev, "GMU firmware error %d\n", in a6xx_hfi_wait_for_ack()
145 error->code); in a6xx_hfi_wait_for_ack()
150 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
157 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
160 return -EINVAL; in a6xx_hfi_wait_for_ack()
175 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_COMMAND_QUEUE]; in a6xx_hfi_send_msg()
179 seqnum = atomic_inc_return(&queue->seqnum) % 0xfff; in a6xx_hfi_send_msg()
181 /* First dword of the message is the message header - fill it in */ in a6xx_hfi_send_msg()
187 DRM_DEV_ERROR(gmu->dev, "Unable to send message %s id %d\n", in a6xx_hfi_send_msg()
199 msg.dbg_buffer_addr = (u32) gmu->debug.iova; in a6xx_hfi_send_gmu_init()
200 msg.dbg_buffer_size = (u32) gmu->debug.size; in a6xx_hfi_send_gmu_init()
223 msg.num_gpu_levels = gmu->nr_gpu_freqs; in a6xx_hfi_send_perf_table_v1()
224 msg.num_gmu_levels = gmu->nr_gmu_freqs; in a6xx_hfi_send_perf_table_v1()
226 for (i = 0; i < gmu->nr_gpu_freqs; i++) { in a6xx_hfi_send_perf_table_v1()
227 msg.gx_votes[i].vote = gmu->gx_arc_votes[i]; in a6xx_hfi_send_perf_table_v1()
228 msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000; in a6xx_hfi_send_perf_table_v1()
231 for (i = 0; i < gmu->nr_gmu_freqs; i++) { in a6xx_hfi_send_perf_table_v1()
232 msg.cx_votes[i].vote = gmu->cx_arc_votes[i]; in a6xx_hfi_send_perf_table_v1()
233 msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000; in a6xx_hfi_send_perf_table_v1()
245 msg.num_gpu_levels = gmu->nr_gpu_freqs; in a6xx_hfi_send_perf_table()
246 msg.num_gmu_levels = gmu->nr_gmu_freqs; in a6xx_hfi_send_perf_table()
248 for (i = 0; i < gmu->nr_gpu_freqs; i++) { in a6xx_hfi_send_perf_table()
249 msg.gx_votes[i].vote = gmu->gx_arc_votes[i]; in a6xx_hfi_send_perf_table()
251 msg.gx_votes[i].freq = gmu->gpu_freqs[i] / 1000; in a6xx_hfi_send_perf_table()
254 for (i = 0; i < gmu->nr_gmu_freqs; i++) { in a6xx_hfi_send_perf_table()
255 msg.cx_votes[i].vote = gmu->cx_arc_votes[i]; in a6xx_hfi_send_perf_table()
256 msg.cx_votes[i].freq = gmu->gmu_freqs[i] / 1000; in a6xx_hfi_send_perf_table()
269 if (!info->bcms[i].name) in a6xx_generate_bw_table()
271 msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name); in a6xx_generate_bw_table()
273 msg->ddr_cmds_num = i; in a6xx_generate_bw_table()
275 for (i = 0; i < gmu->nr_gpu_bws; ++i) in a6xx_generate_bw_table()
276 for (j = 0; j < msg->ddr_cmds_num; j++) in a6xx_generate_bw_table()
277 msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j]; in a6xx_generate_bw_table()
278 msg->bw_level_num = gmu->nr_gpu_bws; in a6xx_generate_bw_table()
281 msg->ddr_wait_bitmask = 0; in a6xx_generate_bw_table()
282 for (j = 0; j < msg->ddr_cmds_num; j++) in a6xx_generate_bw_table()
283 if (msg->ddr_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) in a6xx_generate_bw_table()
284 msg->ddr_wait_bitmask |= BIT(j); in a6xx_generate_bw_table()
287 * These are the CX (CNOC) votes - these are used by the GMU in a6xx_generate_bw_table()
292 msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); in a6xx_generate_bw_table()
293 msg->cnoc_cmds_num = 1; in a6xx_generate_bw_table()
295 msg->cnoc_cmds_data[0][0] = BCM_TCS_CMD(true, false, 0, 0); in a6xx_generate_bw_table()
296 msg->cnoc_cmds_data[1][0] = BCM_TCS_CMD(true, true, 0, BIT(0)); in a6xx_generate_bw_table()
299 msg->cnoc_wait_bitmask = 0; in a6xx_generate_bw_table()
300 for (j = 0; j < msg->cnoc_cmds_num; j++) in a6xx_generate_bw_table()
301 if (msg->cnoc_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) in a6xx_generate_bw_table()
302 msg->cnoc_wait_bitmask |= BIT(j); in a6xx_generate_bw_table()
308 msg->bw_level_num = 1; in a618_build_bw_table()
310 msg->ddr_cmds_num = 3; in a618_build_bw_table()
311 msg->ddr_wait_bitmask = 0x01; in a618_build_bw_table()
313 msg->ddr_cmds_addrs[0] = 0x50000; in a618_build_bw_table()
314 msg->ddr_cmds_addrs[1] = 0x5003c; in a618_build_bw_table()
315 msg->ddr_cmds_addrs[2] = 0x5000c; in a618_build_bw_table()
317 msg->ddr_cmds_data[0][0] = 0x40000000; in a618_build_bw_table()
318 msg->ddr_cmds_data[0][1] = 0x40000000; in a618_build_bw_table()
319 msg->ddr_cmds_data[0][2] = 0x40000000; in a618_build_bw_table()
322 * These are the CX (CNOC) votes - these are used by the GMU but the in a618_build_bw_table()
323 * votes are known and fixed for the target in a618_build_bw_table()
325 msg->cnoc_cmds_num = 1; in a618_build_bw_table()
326 msg->cnoc_wait_bitmask = 0x01; in a618_build_bw_table()
328 msg->cnoc_cmds_addrs[0] = 0x5007c; in a618_build_bw_table()
329 msg->cnoc_cmds_data[0][0] = 0x40000000; in a618_build_bw_table()
330 msg->cnoc_cmds_data[1][0] = 0x60000001; in a618_build_bw_table()
335 msg->bw_level_num = 13; in a619_build_bw_table()
337 msg->ddr_cmds_num = 3; in a619_build_bw_table()
338 msg->ddr_wait_bitmask = 0x0; in a619_build_bw_table()
340 msg->ddr_cmds_addrs[0] = 0x50000; in a619_build_bw_table()
341 msg->ddr_cmds_addrs[1] = 0x50004; in a619_build_bw_table()
342 msg->ddr_cmds_addrs[2] = 0x50080; in a619_build_bw_table()
344 msg->ddr_cmds_data[0][0] = 0x40000000; in a619_build_bw_table()
345 msg->ddr_cmds_data[0][1] = 0x40000000; in a619_build_bw_table()
346 msg->ddr_cmds_data[0][2] = 0x40000000; in a619_build_bw_table()
347 msg->ddr_cmds_data[1][0] = 0x6000030c; in a619_build_bw_table()
348 msg->ddr_cmds_data[1][1] = 0x600000db; in a619_build_bw_table()
349 msg->ddr_cmds_data[1][2] = 0x60000008; in a619_build_bw_table()
350 msg->ddr_cmds_data[2][0] = 0x60000618; in a619_build_bw_table()
351 msg->ddr_cmds_data[2][1] = 0x600001b6; in a619_build_bw_table()
352 msg->ddr_cmds_data[2][2] = 0x60000008; in a619_build_bw_table()
353 msg->ddr_cmds_data[3][0] = 0x60000925; in a619_build_bw_table()
354 msg->ddr_cmds_data[3][1] = 0x60000291; in a619_build_bw_table()
355 msg->ddr_cmds_data[3][2] = 0x60000008; in a619_build_bw_table()
356 msg->ddr_cmds_data[4][0] = 0x60000dc1; in a619_build_bw_table()
357 msg->ddr_cmds_data[4][1] = 0x600003dc; in a619_build_bw_table()
358 msg->ddr_cmds_data[4][2] = 0x60000008; in a619_build_bw_table()
359 msg->ddr_cmds_data[5][0] = 0x600010ad; in a619_build_bw_table()
360 msg->ddr_cmds_data[5][1] = 0x600004ae; in a619_build_bw_table()
361 msg->ddr_cmds_data[5][2] = 0x60000008; in a619_build_bw_table()
362 msg->ddr_cmds_data[6][0] = 0x600014c3; in a619_build_bw_table()
363 msg->ddr_cmds_data[6][1] = 0x600005d4; in a619_build_bw_table()
364 msg->ddr_cmds_data[6][2] = 0x60000008; in a619_build_bw_table()
365 msg->ddr_cmds_data[7][0] = 0x6000176a; in a619_build_bw_table()
366 msg->ddr_cmds_data[7][1] = 0x60000693; in a619_build_bw_table()
367 msg->ddr_cmds_data[7][2] = 0x60000008; in a619_build_bw_table()
368 msg->ddr_cmds_data[8][0] = 0x60001f01; in a619_build_bw_table()
369 msg->ddr_cmds_data[8][1] = 0x600008b5; in a619_build_bw_table()
370 msg->ddr_cmds_data[8][2] = 0x60000008; in a619_build_bw_table()
371 msg->ddr_cmds_data[9][0] = 0x60002940; in a619_build_bw_table()
372 msg->ddr_cmds_data[9][1] = 0x60000b95; in a619_build_bw_table()
373 msg->ddr_cmds_data[9][2] = 0x60000008; in a619_build_bw_table()
374 msg->ddr_cmds_data[10][0] = 0x60002f68; in a619_build_bw_table()
375 msg->ddr_cmds_data[10][1] = 0x60000d50; in a619_build_bw_table()
376 msg->ddr_cmds_data[10][2] = 0x60000008; in a619_build_bw_table()
377 msg->ddr_cmds_data[11][0] = 0x60003700; in a619_build_bw_table()
378 msg->ddr_cmds_data[11][1] = 0x60000f71; in a619_build_bw_table()
379 msg->ddr_cmds_data[11][2] = 0x60000008; in a619_build_bw_table()
380 msg->ddr_cmds_data[12][0] = 0x60003fce; in a619_build_bw_table()
381 msg->ddr_cmds_data[12][1] = 0x600011ea; in a619_build_bw_table()
382 msg->ddr_cmds_data[12][2] = 0x60000008; in a619_build_bw_table()
384 msg->cnoc_cmds_num = 1; in a619_build_bw_table()
385 msg->cnoc_wait_bitmask = 0x0; in a619_build_bw_table()
387 msg->cnoc_cmds_addrs[0] = 0x50054; in a619_build_bw_table()
389 msg->cnoc_cmds_data[0][0] = 0x40000000; in a619_build_bw_table()
398 msg->bw_level_num = 1; in a640_build_bw_table()
400 msg->ddr_cmds_num = 3; in a640_build_bw_table()
401 msg->ddr_wait_bitmask = 0x01; in a640_build_bw_table()
403 msg->ddr_cmds_addrs[0] = 0x50000; in a640_build_bw_table()
404 msg->ddr_cmds_addrs[1] = 0x5003c; in a640_build_bw_table()
405 msg->ddr_cmds_addrs[2] = 0x5000c; in a640_build_bw_table()
407 msg->ddr_cmds_data[0][0] = 0x40000000; in a640_build_bw_table()
408 msg->ddr_cmds_data[0][1] = 0x40000000; in a640_build_bw_table()
409 msg->ddr_cmds_data[0][2] = 0x40000000; in a640_build_bw_table()
412 * These are the CX (CNOC) votes - these are used by the GMU but the in a640_build_bw_table()
413 * votes are known and fixed for the target in a640_build_bw_table()
415 msg->cnoc_cmds_num = 3; in a640_build_bw_table()
416 msg->cnoc_wait_bitmask = 0x01; in a640_build_bw_table()
418 msg->cnoc_cmds_addrs[0] = 0x50034; in a640_build_bw_table()
419 msg->cnoc_cmds_addrs[1] = 0x5007c; in a640_build_bw_table()
420 msg->cnoc_cmds_addrs[2] = 0x5004c; in a640_build_bw_table()
422 msg->cnoc_cmds_data[0][0] = 0x40000000; in a640_build_bw_table()
423 msg->cnoc_cmds_data[0][1] = 0x00000000; in a640_build_bw_table()
424 msg->cnoc_cmds_data[0][2] = 0x40000000; in a640_build_bw_table()
426 msg->cnoc_cmds_data[1][0] = 0x60000001; in a640_build_bw_table()
427 msg->cnoc_cmds_data[1][1] = 0x20000001; in a640_build_bw_table()
428 msg->cnoc_cmds_data[1][2] = 0x60000001; in a640_build_bw_table()
437 msg->bw_level_num = 1; in a650_build_bw_table()
439 msg->ddr_cmds_num = 3; in a650_build_bw_table()
440 msg->ddr_wait_bitmask = 0x01; in a650_build_bw_table()
442 msg->ddr_cmds_addrs[0] = 0x50000; in a650_build_bw_table()
443 msg->ddr_cmds_addrs[1] = 0x50004; in a650_build_bw_table()
444 msg->ddr_cmds_addrs[2] = 0x5007c; in a650_build_bw_table()
446 msg->ddr_cmds_data[0][0] = 0x40000000; in a650_build_bw_table()
447 msg->ddr_cmds_data[0][1] = 0x40000000; in a650_build_bw_table()
448 msg->ddr_cmds_data[0][2] = 0x40000000; in a650_build_bw_table()
451 * These are the CX (CNOC) votes - these are used by the GMU but the in a650_build_bw_table()
452 * votes are known and fixed for the target in a650_build_bw_table()
454 msg->cnoc_cmds_num = 1; in a650_build_bw_table()
455 msg->cnoc_wait_bitmask = 0x01; in a650_build_bw_table()
457 msg->cnoc_cmds_addrs[0] = 0x500a4; in a650_build_bw_table()
458 msg->cnoc_cmds_data[0][0] = 0x40000000; in a650_build_bw_table()
459 msg->cnoc_cmds_data[1][0] = 0x60000001; in a650_build_bw_table()
468 msg->bw_level_num = 1; in a690_build_bw_table()
470 msg->ddr_cmds_num = 3; in a690_build_bw_table()
471 msg->ddr_wait_bitmask = 0x01; in a690_build_bw_table()
473 msg->ddr_cmds_addrs[0] = 0x50004; in a690_build_bw_table()
474 msg->ddr_cmds_addrs[1] = 0x50000; in a690_build_bw_table()
475 msg->ddr_cmds_addrs[2] = 0x500ac; in a690_build_bw_table()
477 msg->ddr_cmds_data[0][0] = 0x40000000; in a690_build_bw_table()
478 msg->ddr_cmds_data[0][1] = 0x40000000; in a690_build_bw_table()
479 msg->ddr_cmds_data[0][2] = 0x40000000; in a690_build_bw_table()
482 * These are the CX (CNOC) votes - these are used by the GMU but the in a690_build_bw_table()
483 * votes are known and fixed for the target in a690_build_bw_table()
485 msg->cnoc_cmds_num = 1; in a690_build_bw_table()
486 msg->cnoc_wait_bitmask = 0x01; in a690_build_bw_table()
488 msg->cnoc_cmds_addrs[0] = 0x5003c; in a690_build_bw_table()
489 msg->cnoc_cmds_data[0][0] = 0x40000000; in a690_build_bw_table()
490 msg->cnoc_cmds_data[1][0] = 0x60000001; in a690_build_bw_table()
499 msg->bw_level_num = 1; in a660_build_bw_table()
501 msg->ddr_cmds_num = 3; in a660_build_bw_table()
502 msg->ddr_wait_bitmask = 0x01; in a660_build_bw_table()
504 msg->ddr_cmds_addrs[0] = 0x50004; in a660_build_bw_table()
505 msg->ddr_cmds_addrs[1] = 0x500a0; in a660_build_bw_table()
506 msg->ddr_cmds_addrs[2] = 0x50000; in a660_build_bw_table()
508 msg->ddr_cmds_data[0][0] = 0x40000000; in a660_build_bw_table()
509 msg->ddr_cmds_data[0][1] = 0x40000000; in a660_build_bw_table()
510 msg->ddr_cmds_data[0][2] = 0x40000000; in a660_build_bw_table()
513 * These are the CX (CNOC) votes - these are used by the GMU but the in a660_build_bw_table()
514 * votes are known and fixed for the target in a660_build_bw_table()
516 msg->cnoc_cmds_num = 1; in a660_build_bw_table()
517 msg->cnoc_wait_bitmask = 0x01; in a660_build_bw_table()
519 msg->cnoc_cmds_addrs[0] = 0x50070; in a660_build_bw_table()
520 msg->cnoc_cmds_data[0][0] = 0x40000000; in a660_build_bw_table()
521 msg->cnoc_cmds_data[1][0] = 0x60000001; in a660_build_bw_table()
530 msg->bw_level_num = 1; in a663_build_bw_table()
532 msg->ddr_cmds_num = 3; in a663_build_bw_table()
533 msg->ddr_wait_bitmask = 0x07; in a663_build_bw_table()
535 msg->ddr_cmds_addrs[0] = 0x50004; in a663_build_bw_table()
536 msg->ddr_cmds_addrs[1] = 0x50000; in a663_build_bw_table()
537 msg->ddr_cmds_addrs[2] = 0x500b4; in a663_build_bw_table()
539 msg->ddr_cmds_data[0][0] = 0x40000000; in a663_build_bw_table()
540 msg->ddr_cmds_data[0][1] = 0x40000000; in a663_build_bw_table()
541 msg->ddr_cmds_data[0][2] = 0x40000000; in a663_build_bw_table()
544 * These are the CX (CNOC) votes - these are used by the GMU but the in a663_build_bw_table()
545 * votes are known and fixed for the target in a663_build_bw_table()
547 msg->cnoc_cmds_num = 1; in a663_build_bw_table()
548 msg->cnoc_wait_bitmask = 0x01; in a663_build_bw_table()
550 msg->cnoc_cmds_addrs[0] = 0x50058; in a663_build_bw_table()
551 msg->cnoc_cmds_data[0][0] = 0x40000000; in a663_build_bw_table()
552 msg->cnoc_cmds_data[1][0] = 0x60000001; in a663_build_bw_table()
561 msg->bw_level_num = 1; in adreno_7c3_build_bw_table()
563 msg->ddr_cmds_num = 3; in adreno_7c3_build_bw_table()
564 msg->ddr_wait_bitmask = 0x07; in adreno_7c3_build_bw_table()
566 msg->ddr_cmds_addrs[0] = 0x50004; in adreno_7c3_build_bw_table()
567 msg->ddr_cmds_addrs[1] = 0x50000; in adreno_7c3_build_bw_table()
568 msg->ddr_cmds_addrs[2] = 0x50088; in adreno_7c3_build_bw_table()
570 msg->ddr_cmds_data[0][0] = 0x40000000; in adreno_7c3_build_bw_table()
571 msg->ddr_cmds_data[0][1] = 0x40000000; in adreno_7c3_build_bw_table()
572 msg->ddr_cmds_data[0][2] = 0x40000000; in adreno_7c3_build_bw_table()
575 * These are the CX (CNOC) votes - these are used by the GMU but the in adreno_7c3_build_bw_table()
576 * votes are known and fixed for the target in adreno_7c3_build_bw_table()
578 msg->cnoc_cmds_num = 1; in adreno_7c3_build_bw_table()
579 msg->cnoc_wait_bitmask = 0x01; in adreno_7c3_build_bw_table()
581 msg->cnoc_cmds_addrs[0] = 0x5006c; in adreno_7c3_build_bw_table()
582 msg->cnoc_cmds_data[0][0] = 0x40000000; in adreno_7c3_build_bw_table()
583 msg->cnoc_cmds_data[1][0] = 0x60000001; in adreno_7c3_build_bw_table()
588 msg->bw_level_num = 12; in a730_build_bw_table()
590 msg->ddr_cmds_num = 3; in a730_build_bw_table()
591 msg->ddr_wait_bitmask = 0x7; in a730_build_bw_table()
593 msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0"); in a730_build_bw_table()
594 msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0"); in a730_build_bw_table()
595 msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV"); in a730_build_bw_table()
597 msg->ddr_cmds_data[0][0] = 0x40000000; in a730_build_bw_table()
598 msg->ddr_cmds_data[0][1] = 0x40000000; in a730_build_bw_table()
599 msg->ddr_cmds_data[0][2] = 0x40000000; in a730_build_bw_table()
600 msg->ddr_cmds_data[1][0] = 0x600002e8; in a730_build_bw_table()
601 msg->ddr_cmds_data[1][1] = 0x600003d0; in a730_build_bw_table()
602 msg->ddr_cmds_data[1][2] = 0x60000008; in a730_build_bw_table()
603 msg->ddr_cmds_data[2][0] = 0x6000068d; in a730_build_bw_table()
604 msg->ddr_cmds_data[2][1] = 0x6000089a; in a730_build_bw_table()
605 msg->ddr_cmds_data[2][2] = 0x60000008; in a730_build_bw_table()
606 msg->ddr_cmds_data[3][0] = 0x600007f2; in a730_build_bw_table()
607 msg->ddr_cmds_data[3][1] = 0x60000a6e; in a730_build_bw_table()
608 msg->ddr_cmds_data[3][2] = 0x60000008; in a730_build_bw_table()
609 msg->ddr_cmds_data[4][0] = 0x600009e5; in a730_build_bw_table()
610 msg->ddr_cmds_data[4][1] = 0x60000cfd; in a730_build_bw_table()
611 msg->ddr_cmds_data[4][2] = 0x60000008; in a730_build_bw_table()
612 msg->ddr_cmds_data[5][0] = 0x60000b29; in a730_build_bw_table()
613 msg->ddr_cmds_data[5][1] = 0x60000ea6; in a730_build_bw_table()
614 msg->ddr_cmds_data[5][2] = 0x60000008; in a730_build_bw_table()
615 msg->ddr_cmds_data[6][0] = 0x60001698; in a730_build_bw_table()
616 msg->ddr_cmds_data[6][1] = 0x60001da8; in a730_build_bw_table()
617 msg->ddr_cmds_data[6][2] = 0x60000008; in a730_build_bw_table()
618 msg->ddr_cmds_data[7][0] = 0x600018d2; in a730_build_bw_table()
619 msg->ddr_cmds_data[7][1] = 0x60002093; in a730_build_bw_table()
620 msg->ddr_cmds_data[7][2] = 0x60000008; in a730_build_bw_table()
621 msg->ddr_cmds_data[8][0] = 0x60001e66; in a730_build_bw_table()
622 msg->ddr_cmds_data[8][1] = 0x600027e6; in a730_build_bw_table()
623 msg->ddr_cmds_data[8][2] = 0x60000008; in a730_build_bw_table()
624 msg->ddr_cmds_data[9][0] = 0x600027c2; in a730_build_bw_table()
625 msg->ddr_cmds_data[9][1] = 0x6000342f; in a730_build_bw_table()
626 msg->ddr_cmds_data[9][2] = 0x60000008; in a730_build_bw_table()
627 msg->ddr_cmds_data[10][0] = 0x60002e71; in a730_build_bw_table()
628 msg->ddr_cmds_data[10][1] = 0x60003cf5; in a730_build_bw_table()
629 msg->ddr_cmds_data[10][2] = 0x60000008; in a730_build_bw_table()
630 msg->ddr_cmds_data[11][0] = 0x600030ae; in a730_build_bw_table()
631 msg->ddr_cmds_data[11][1] = 0x60003fe5; in a730_build_bw_table()
632 msg->ddr_cmds_data[11][2] = 0x60000008; in a730_build_bw_table()
634 msg->cnoc_cmds_num = 1; in a730_build_bw_table()
635 msg->cnoc_wait_bitmask = 0x1; in a730_build_bw_table()
637 msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); in a730_build_bw_table()
638 msg->cnoc_cmds_data[0][0] = 0x40000000; in a730_build_bw_table()
639 msg->cnoc_cmds_data[1][0] = 0x60000001; in a730_build_bw_table()
644 msg->bw_level_num = 1; in a740_build_bw_table()
646 msg->ddr_cmds_num = 3; in a740_build_bw_table()
647 msg->ddr_wait_bitmask = 0x7; in a740_build_bw_table()
649 msg->ddr_cmds_addrs[0] = cmd_db_read_addr("SH0"); in a740_build_bw_table()
650 msg->ddr_cmds_addrs[1] = cmd_db_read_addr("MC0"); in a740_build_bw_table()
651 msg->ddr_cmds_addrs[2] = cmd_db_read_addr("ACV"); in a740_build_bw_table()
653 msg->ddr_cmds_data[0][0] = 0x40000000; in a740_build_bw_table()
654 msg->ddr_cmds_data[0][1] = 0x40000000; in a740_build_bw_table()
655 msg->ddr_cmds_data[0][2] = 0x40000000; in a740_build_bw_table()
659 msg->cnoc_cmds_num = 1; in a740_build_bw_table()
660 msg->cnoc_wait_bitmask = 0x1; in a740_build_bw_table()
662 msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); in a740_build_bw_table()
663 msg->cnoc_cmds_data[0][0] = 0x40000000; in a740_build_bw_table()
664 msg->cnoc_cmds_data[1][0] = 0x60000001; in a740_build_bw_table()
670 msg->bw_level_num = 1; in a6xx_build_bw_table()
672 msg->ddr_cmds_num = 3; in a6xx_build_bw_table()
673 msg->ddr_wait_bitmask = 0x07; in a6xx_build_bw_table()
675 msg->ddr_cmds_addrs[0] = 0x50000; in a6xx_build_bw_table()
676 msg->ddr_cmds_addrs[1] = 0x5005c; in a6xx_build_bw_table()
677 msg->ddr_cmds_addrs[2] = 0x5000c; in a6xx_build_bw_table()
679 msg->ddr_cmds_data[0][0] = 0x40000000; in a6xx_build_bw_table()
680 msg->ddr_cmds_data[0][1] = 0x40000000; in a6xx_build_bw_table()
681 msg->ddr_cmds_data[0][2] = 0x40000000; in a6xx_build_bw_table()
685 * sdm845 GMU are known and fixed so we can hard code them. in a6xx_build_bw_table()
688 msg->cnoc_cmds_num = 3; in a6xx_build_bw_table()
689 msg->cnoc_wait_bitmask = 0x05; in a6xx_build_bw_table()
691 msg->cnoc_cmds_addrs[0] = 0x50034; in a6xx_build_bw_table()
692 msg->cnoc_cmds_addrs[1] = 0x5007c; in a6xx_build_bw_table()
693 msg->cnoc_cmds_addrs[2] = 0x5004c; in a6xx_build_bw_table()
695 msg->cnoc_cmds_data[0][0] = 0x40000000; in a6xx_build_bw_table()
696 msg->cnoc_cmds_data[0][1] = 0x00000000; in a6xx_build_bw_table()
697 msg->cnoc_cmds_data[0][2] = 0x40000000; in a6xx_build_bw_table()
699 msg->cnoc_cmds_data[1][0] = 0x60000001; in a6xx_build_bw_table()
700 msg->cnoc_cmds_data[1][1] = 0x20000001; in a6xx_build_bw_table()
701 msg->cnoc_cmds_data[1][2] = 0x60000001; in a6xx_build_bw_table()
709 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; in a6xx_hfi_send_bw_table()
710 const struct a6xx_info *info = adreno_gpu->info->a6xx; in a6xx_hfi_send_bw_table()
712 if (gmu->bw_table) in a6xx_hfi_send_bw_table()
715 msg = devm_kzalloc(gmu->dev, sizeof(*msg), GFP_KERNEL); in a6xx_hfi_send_bw_table()
717 return -ENOMEM; in a6xx_hfi_send_bw_table()
719 if (info->bcms && gmu->nr_gpu_bws > 1) in a6xx_hfi_send_bw_table()
744 gmu->bw_table = msg; in a6xx_hfi_send_bw_table()
747 return a6xx_hfi_send_msg(gmu, HFI_H2F_MSG_BW_TABLE, gmu->bw_table, sizeof(*(gmu->bw_table)), in a6xx_hfi_send_bw_table()
791 /* TODO: should freq and bw fields be non-zero ? */ in a6xx_hfi_send_prep_slumber()
836 if (gmu->legacy) in a6xx_hfi_start()
867 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_hfi_stop()
868 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_hfi_stop()
870 if (!queue->header) in a6xx_hfi_stop()
873 if (queue->header->read_index != queue->header->write_index) in a6xx_hfi_stop()
874 DRM_DEV_ERROR(gmu->dev, "HFI queue %d is not empty\n", i); in a6xx_hfi_stop()
876 queue->header->read_index = 0; in a6xx_hfi_stop()
877 queue->header->write_index = 0; in a6xx_hfi_stop()
879 memset(&queue->history, 0xff, sizeof(queue->history)); in a6xx_hfi_stop()
880 queue->history_idx = 0; in a6xx_hfi_stop()
885 struct a6xx_hfi_queue_header *header, void *virt, u64 iova, in a6xx_hfi_queue_init() argument
888 spin_lock_init(&queue->lock); in a6xx_hfi_queue_init()
889 queue->header = header; in a6xx_hfi_queue_init()
890 queue->data = virt; in a6xx_hfi_queue_init()
891 atomic_set(&queue->seqnum, 0); in a6xx_hfi_queue_init()
893 memset(&queue->history, 0xff, sizeof(queue->history)); in a6xx_hfi_queue_init()
894 queue->history_idx = 0; in a6xx_hfi_queue_init()
896 /* Set up the shared memory header */ in a6xx_hfi_queue_init()
897 header->iova = iova; in a6xx_hfi_queue_init()
898 header->type = 10 << 8 | id; in a6xx_hfi_queue_init()
899 header->status = 1; in a6xx_hfi_queue_init()
900 header->size = SZ_4K >> 2; in a6xx_hfi_queue_init()
901 header->msg_size = 0; in a6xx_hfi_queue_init()
902 header->dropped = 0; in a6xx_hfi_queue_init()
903 header->rx_watermark = 1; in a6xx_hfi_queue_init()
904 header->tx_watermark = 1; in a6xx_hfi_queue_init()
905 header->rx_request = 1; in a6xx_hfi_queue_init()
906 header->tx_request = 0; in a6xx_hfi_queue_init()
907 header->read_index = 0; in a6xx_hfi_queue_init()
908 header->write_index = 0; in a6xx_hfi_queue_init()
913 struct a6xx_gmu_bo *hfi = &gmu->hfi; in a6xx_hfi_init()
914 struct a6xx_hfi_queue_table_header *table = hfi->virt; in a6xx_hfi_init()
915 struct a6xx_hfi_queue_header *headers = hfi->virt + sizeof(*table); in a6xx_hfi_init()
920 * The table size is the size of the table header plus all of the queue in a6xx_hfi_init()
924 table_size += (ARRAY_SIZE(gmu->queues) * in a6xx_hfi_init()
927 table->version = 0; in a6xx_hfi_init()
928 table->size = table_size; in a6xx_hfi_init()
929 /* First queue header is located immediately after the table header */ in a6xx_hfi_init()
930 table->qhdr0_offset = sizeof(*table) >> 2; in a6xx_hfi_init()
931 table->qhdr_size = sizeof(struct a6xx_hfi_queue_header) >> 2; in a6xx_hfi_init()
932 table->num_queues = ARRAY_SIZE(gmu->queues); in a6xx_hfi_init()
933 table->active_queues = ARRAY_SIZE(gmu->queues); in a6xx_hfi_init()
937 a6xx_hfi_queue_init(&gmu->queues[0], &headers[0], hfi->virt + offset, in a6xx_hfi_init()
938 hfi->iova + offset, 0); in a6xx_hfi_init()
942 a6xx_hfi_queue_init(&gmu->queues[1], &headers[1], hfi->virt + offset, in a6xx_hfi_init()
943 hfi->iova + offset, gmu->legacy ? 4 : 1); in a6xx_hfi_init()