28 static void a3xx_dump(struct msm_gpu *gpu);
29 static bool a3xx_idle(struct msm_gpu *gpu);
31 static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)  in a3xx_submit()  argument
69 	/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */  in a3xx_submit()
82 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a3xx_submit()
85 static bool a3xx_me_init(struct msm_gpu *gpu)  in a3xx_me_init()  argument
87 	struct msm_ringbuffer *ring = gpu->rb[0];  in a3xx_me_init()
108 	adreno_flush(gpu, ring, REG_AXXX_CP_RB_WPTR);  in a3xx_me_init()
109 	return a3xx_idle(gpu);  in a3xx_me_init()
112 static int a3xx_hw_init(struct msm_gpu *gpu)  in a3xx_hw_init()  argument
114 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a3xx_hw_init()
119 	DBG("%s", gpu->name);  in a3xx_hw_init()
123 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
124 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
125 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
126 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
127 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
128 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
129 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
131 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);  in a3xx_hw_init()
133 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
135 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);  in a3xx_hw_init()
136 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);  in a3xx_hw_init()
138 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818);  in a3xx_hw_init()
139 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818);  in a3xx_hw_init()
140 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018);  in a3xx_hw_init()
141 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018);  in a3xx_hw_init()
142 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303);  in a3xx_hw_init()
143 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
145 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
146 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a);  in a3xx_hw_init()
147 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a);  in a3xx_hw_init()
149 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
150 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010);  in a3xx_hw_init()
151 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010);  in a3xx_hw_init()
154 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
155 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
156 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
157 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
158 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
159 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010);  in a3xx_hw_init()
160 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010);  in a3xx_hw_init()
162 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff);  in a3xx_hw_init()
164 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
166 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);  in a3xx_hw_init()
167 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);  in a3xx_hw_init()
169 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);  in a3xx_hw_init()
170 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
179 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);  in a3xx_hw_init()
180 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
182 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);  in a3xx_hw_init()
183 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
185 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);  in a3xx_hw_init()
189 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
190 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);  in a3xx_hw_init()
191 		gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
192 		gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
193 		gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303);  in a3xx_hw_init()
194 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818);  in a3xx_hw_init()
195 		gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818);  in a3xx_hw_init()
197 		gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f);  in a3xx_hw_init()
199 		gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030);  in a3xx_hw_init()
201 		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001);  in a3xx_hw_init()
203 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f);  in a3xx_hw_init()
204 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f);  in a3xx_hw_init()
206 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f);  in a3xx_hw_init()
207 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);  in a3xx_hw_init()
209 		 * higher frequency than GPU:  in a3xx_hw_init()
211 		gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);  in a3xx_hw_init()
217 	/* Make all blocks contribute to the GPU BUSY perf counter: */  in a3xx_hw_init()
218 	gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff);  in a3xx_hw_init()
221 	gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10);  in a3xx_hw_init()
222 	gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10);  in a3xx_hw_init()
227 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001);  in a3xx_hw_init()
230 	gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff);  in a3xx_hw_init()
233 	gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000);  in a3xx_hw_init()
238 	gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff);  in a3xx_hw_init()
241 	gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);  in a3xx_hw_init()
247 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);  in a3xx_hw_init()
249 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff);  in a3xx_hw_init()
251 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);  in a3xx_hw_init()
253 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff);  in a3xx_hw_init()
256 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455);  in a3xx_hw_init()
258 		gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000);  in a3xx_hw_init()
262 		gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR,  in a3xx_hw_init()
267 	gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01);  in a3xx_hw_init()
270 	for (i = 0; i < gpu->num_perfcntrs; i++) {  in a3xx_hw_init()
271 		const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i];  in a3xx_hw_init()
272 		gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val);  in a3xx_hw_init()
275 	gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK);  in a3xx_hw_init()
277 	ret = adreno_hw_init(gpu);  in a3xx_hw_init()
285 	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,  in a3xx_hw_init()
289 	gpu_write(gpu, REG_AXXX_CP_RB_BASE, lower_32_bits(gpu->rb[0]->iova));  in a3xx_hw_init()
292 	gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007);  in a3xx_hw_init()
295 	gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040);  in a3xx_hw_init()
296 	gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080);  in a3xx_hw_init()
297 	gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc);  in a3xx_hw_init()
298 	gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108);  in a3xx_hw_init()
299 	gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140);  in a3xx_hw_init()
300 	gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400);  in a3xx_hw_init()
303 	gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700);  in a3xx_hw_init()
304 	gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8);  in a3xx_hw_init()
305 	gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0);  in a3xx_hw_init()
306 	gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178);  in a3xx_hw_init()
307 	gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180);  in a3xx_hw_init()
310 	gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300);  in a3xx_hw_init()
313 	gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000);  in a3xx_hw_init()
326 	gpu_write(gpu, REG_AXXX_CP_DEBUG,  in a3xx_hw_init()
329 	gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0);  in a3xx_hw_init()
331 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);  in a3xx_hw_init()
338 	gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);  in a3xx_hw_init()
340 		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);  in a3xx_hw_init()
347 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,  in a3xx_hw_init()
357 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008);  in a3xx_hw_init()
361 	gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0);  in a3xx_hw_init()
363 	return a3xx_me_init(gpu) ? 0 : -EINVAL;  in a3xx_hw_init()
366 static void a3xx_recover(struct msm_gpu *gpu)  in a3xx_recover()  argument
370 	adreno_dump_info(gpu);  in a3xx_recover()
374 			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));  in a3xx_recover()
377 	/* dump registers before resetting gpu, if enabled: */  in a3xx_recover()
379 		a3xx_dump(gpu);  in a3xx_recover()
381 	gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1);  in a3xx_recover()
382 	gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD);  in a3xx_recover()
383 	gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0);  in a3xx_recover()
384 	adreno_recover(gpu);  in a3xx_recover()
387 static void a3xx_destroy(struct msm_gpu *gpu)  in a3xx_destroy()  argument
389 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);  in a3xx_destroy()
392 	DBG("%s", gpu->name);  in a3xx_destroy()
401 static bool a3xx_idle(struct msm_gpu *gpu)  in a3xx_idle()  argument
404 	if (!adreno_idle(gpu, gpu->rb[0]))  in a3xx_idle()
407 	/* then wait for GPU to finish: */  in a3xx_idle()
408 	if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) &  in a3xx_idle()
410 		DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name);  in a3xx_idle()
412 		/* TODO maybe we need to reset GPU here to recover from hang? */  in a3xx_idle()
419 static irqreturn_t a3xx_irq(struct msm_gpu *gpu)  in a3xx_irq()  argument
423 	status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS);  in a3xx_irq()
424 	DBG("%s: %08x", gpu->name, status);  in a3xx_irq()
428 	gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);  in a3xx_irq()
430 	msm_gpu_retire(gpu);  in a3xx_irq()
474 static void a3xx_dump(struct msm_gpu *gpu)  in a3xx_dump()  argument
477 			gpu_read(gpu, REG_A3XX_RBBM_STATUS));  in a3xx_dump()
478 	adreno_dump(gpu);  in a3xx_dump()
481 static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu)  in a3xx_gpu_state_get()  argument
488 	adreno_gpu_state_get(gpu, state);  in a3xx_gpu_state_get()
490 	state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS);  in a3xx_gpu_state_get()
495 static u64 a3xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)  in a3xx_gpu_busy()  argument
499 	busy_cycles = gpu_read64(gpu, REG_A3XX_RBBM_PERFCTR_RBBM_1_LO);  in a3xx_gpu_busy()
500 	*out_sample_rate = clk_get_rate(gpu->core_clk);  in a3xx_gpu_busy()
505 static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)  in a3xx_get_rptr()  argument
507 	ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR);  in a3xx_get_rptr()
545 	struct msm_gpu *gpu;  in a3xx_gpu_init()  local
565 	gpu = &adreno_gpu->base;  in a3xx_gpu_init()
567 	gpu->perfcntrs = perfcntrs;  in a3xx_gpu_init()
568 	gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);  in a3xx_gpu_init()
584 	if (!gpu->aspace) {  in a3xx_gpu_init()
585 		/* TODO we think it is possible to configure the GPU to  in a3xx_gpu_init()
620 	icc_set_bw(icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a3xx_gpu_init()
621 	icc_set_bw(ocmem_icc_path, 0, Bps_to_icc(gpu->fast_rate) * 8);  in a3xx_gpu_init()
623 	return gpu;  in a3xx_gpu_init()