Lines Matching +full:burst +full:- +full:wrap
1 // SPDX-License-Identifier: GPL-2.0-or-later
24 * - OSD1 RGB565/RGB888/xRGB8888 scanout
25 * - RGB conversion to x/cb/cr
26 * - Progressive or Interlace buffer scanout
27 * - OSD1 Commit on Vsync
28 * - HDR OSD matrix for GXL/GXM
32 * - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
33 * - YUV4:2:2 Y0CbY1Cr scanout
34 * - Conversion to YUV 4:4:4 from 4:2:2 input
35 * - Colorkey Alpha matching
36 * - Big endian scanout
37 * - X/Y reverse scanout
38 * - Global alpha setup
39 * - OSD2 support, would need interlace switching on vsync
40 * - OSD1 full scaling to support TV overscan
65 COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
66 COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
84 /* VPP WRAP OSD1 matrix */ in meson_viu_set_g12a_osd1_matrix()
86 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
88 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
90 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01)); in meson_viu_set_g12a_osd1_matrix()
92 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10)); in meson_viu_set_g12a_osd1_matrix()
94 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12)); in meson_viu_set_g12a_osd1_matrix()
96 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21)); in meson_viu_set_g12a_osd1_matrix()
98 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22)); in meson_viu_set_g12a_osd1_matrix()
101 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_g12a_osd1_matrix()
103 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2)); in meson_viu_set_g12a_osd1_matrix()
106 priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_viu_set_g12a_osd1_matrix()
116 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1)); in meson_viu_set_osd_matrix()
118 priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2)); in meson_viu_set_osd_matrix()
120 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01)); in meson_viu_set_osd_matrix()
122 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10)); in meson_viu_set_osd_matrix()
124 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12)); in meson_viu_set_osd_matrix()
126 priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21)); in meson_viu_set_osd_matrix()
130 priv->io_base + in meson_viu_set_osd_matrix()
133 priv->io_base + in meson_viu_set_osd_matrix()
136 priv->io_base + in meson_viu_set_osd_matrix()
138 writel(m[17] & 0x1fff, priv->io_base + in meson_viu_set_osd_matrix()
141 writel((m[11] & 0x1fff) << 16, priv->io_base + in meson_viu_set_osd_matrix()
145 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1)); in meson_viu_set_osd_matrix()
147 priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2)); in meson_viu_set_osd_matrix()
150 priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
152 priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42)); in meson_viu_set_osd_matrix()
156 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
158 priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL)); in meson_viu_set_osd_matrix()
165 (m[i * 2 + 1] & 0x1fff), priv->io_base + in meson_viu_set_osd_matrix()
169 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
171 priv->io_base + _REG(VIU_OSD1_EOTF_CTL)); in meson_viu_set_osd_matrix()
200 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
206 writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
217 writel(b_map[OSD_OETF_LUT_SIZE - 1], in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
222 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
225 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
227 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
231 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
233 writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
238 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
242 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
244 writel(b_map[OSD_EOTF_LUT_SIZE - 1], in meson_viu_set_osd_lut()
245 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
249 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
252 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
255 priv->io_base + _REG(ctrl_port)); in meson_viu_set_osd_lut()
321 priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_osd1_reset()
323 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_osd1_reset()
327 priv->io_base + _REG(VIU_SW_RESET)); in meson_viu_osd1_reset()
329 priv->io_base + _REG(VIU_SW_RESET)); in meson_viu_osd1_reset()
333 priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_osd1_reset()
335 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_osd1_reset()
368 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
370 switch (priv->afbcd.format) { in meson_viu_g12a_enable_osd1_afbc()
383 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
388 priv->io_base + _REG(OSD_PATH_MISC_CTRL)); in meson_viu_g12a_enable_osd1_afbc()
395 priv->io_base + _REG(OSD_PATH_MISC_CTRL)); in meson_viu_g12a_disable_osd1_afbc()
399 priv->io_base + _REG(VIU_OSD1_MALI_UNPACK_CTRL)); in meson_viu_g12a_disable_osd1_afbc()
405 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_viu_gxm_enable_osd1_afbc()
411 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_viu_gxm_disable_osd1_afbc()
420 priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); in meson_viu_init()
422 priv->io_base + _REG(VIU_OSD2_CTRL_STAT)); in meson_viu_init()
431 /* fix green/pink color distortion from vendor u-boot */ in meson_viu_init()
434 priv->io_base + _REG(OSD1_HDR2_CTRL)); in meson_viu_init()
440 VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ in meson_viu_init()
448 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); in meson_viu_init()
449 writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); in meson_viu_init()
454 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); in meson_viu_init()
457 priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); in meson_viu_init()
462 priv->io_base + _REG(VIU_MISC_CTRL0)); in meson_viu_init()
463 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE)); in meson_viu_init()
466 priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE)); in meson_viu_init()
468 priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE)); in meson_viu_init()
481 writel_relaxed(val, priv->io_base + _REG(VIU_OSD_BLEND_CTRL)); in meson_viu_init()
484 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL)); in meson_viu_init()
486 priv->io_base + _REG(OSD2_BLEND_SRC_CTRL)); in meson_viu_init()
487 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL)); in meson_viu_init()
488 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL)); in meson_viu_init()
490 priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0)); in meson_viu_init()
492 priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA)); in meson_viu_init()
495 priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_viu_init()
503 priv->viu.osd1_enabled = false; in meson_viu_init()
504 priv->viu.osd1_commit = false; in meson_viu_init()
505 priv->viu.osd1_interlace = false; in meson_viu_init()