473 static inline unsigned int pll_od_to_reg(unsigned int od)  in pll_od_to_reg()  argument
475 	switch (od) {  in pll_od_to_reg()
700 				       unsigned int *od)  in meson_hdmi_pll_find_params()  argument
703 	for (*od = 16 ; *od > 1 ; *od >>= 1) {  in meson_hdmi_pll_find_params()
704 		*m = meson_hdmi_pll_get_m(priv, freq * *od);  in meson_hdmi_pll_find_params()
707 		*frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);  in meson_hdmi_pll_find_params()
709 		DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",  in meson_hdmi_pll_find_params()
710 				 freq, *m, *frac, *od);  in meson_hdmi_pll_find_params()
719 /* pll_freq is the frequency after the OD dividers */
723 	unsigned int od, m, frac;  in meson_vclk_dmt_supported_freq()  local
735 	if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))  in meson_vclk_dmt_supported_freq()
742 /* pll_freq is the frequency after the OD dividers */
746 	unsigned int od, m, frac, od1, od2, od3;  in meson_hdmi_pll_generic_set()  local
748 	if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {  in meson_hdmi_pll_generic_set()
751 		if (od < 4) {  in meson_hdmi_pll_generic_set()
755 			od2 = od / 4;  in meson_hdmi_pll_generic_set()
756 			od1 = od / od2;  in meson_hdmi_pll_generic_set()
759 		DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",  in meson_hdmi_pll_generic_set()
1043 		 * - automatic PLL freq + OD management  in meson_vclk_setup()