Lines Matching +full:0 +full:x3c8
12 /* [31: 4] Reserved. Default 0.
14 * 1=Assert SW reset of timing feature. 0=Release reset.
16 * 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset.
18 * 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset.
19 * [0] RW dwc_rst_n: Default 1.
20 * 1=Assert SW reset on IP core. 0=Release reset.
22 #define MIPI_DSI_TOP_SW_RESET 0x3c0
24 #define MIPI_DSI_TOP_SW_RESET_DWC BIT(0)
29 /* [31: 5] Reserved. Default 0.
30 * [4] RW manual_edpihalt: Default 0.
31 * 1=Manual suspend VencL; 0=do not suspend VencL.
32 * [3] RW auto_edpihalt_en: Default 0.
34 * 0=IP's edpihalt signal does not affect VencL.
35 * [2] RW clock_freerun: Apply to auto-clock gate only. Default 0.
36 * 0=Default, use auto-clock gating to save power;
39 * have auto-clock gating. 1=Enable pixclk. Default 0.
40 * [0] RW enable_sysclk: A manual clock gate option, due to DWC IP does not
41 * have auto-clock gating. 1=Enable sysclk. Default 0.
43 #define MIPI_DSI_TOP_CLK_CNTL 0x3c4
45 #define MIPI_DSI_TOP_CLK_SYSCLK_EN BIT(0)
48 /* [31:24] Reserved. Default 0.
49 * [23:20] RW dpi_color_mode: Define DPI pixel format. Default 0.
50 * 0=16-bit RGB565 config 1;
61 * 11=12-bit YCbCr 4:2:0.
62 * [19] Reserved. Default 0.
63 * [18:16] RW in_color_mode: Define VENC data width. Default 0.
64 * 0=30-bit pixel;
68 * [15:14] RW chroma_subsample: Define method of chroma subsampling. Default 0.
70 * 0=Use even pixel's chroma;
74 * 0=comp0; 1=comp1; 2=comp2.
76 * 0=comp0; 1=comp1; 2=comp2.
77 * [9: 8] RW comp0_sel: Select which component to be Y or R: Default 0.
78 * 0=comp0; 1=comp1; 2=comp2.
79 * [7] Reserved. Default 0.
80 * [6] RW de_pol: Default 0.
82 * [5] RW hsync_pol: Default 0.
84 * [4] RW vsync_pol: Default 0.
86 * [3] RW dpicolorm: Signal to IP. Default 0.
87 * [2] RW dpishutdn: Signal to IP. Default 0.
88 * [1] Reserved. Default 0.
89 * [0] Reserved. Default 0.
91 #define MIPI_DSI_TOP_CNTL 0x3c8
94 #define VENC_IN_COLOR_30B 0x0
95 #define VENC_IN_COLOR_24B 0x1
96 #define VENC_IN_COLOR_18B 0x2
97 #define VENC_IN_COLOR_16B 0x3
100 #define DPI_COLOR_16BIT_CFG_1 0
125 #define MIPI_DSI_TOP_SUSPEND_CNTL 0x3cc
126 #define MIPI_DSI_TOP_SUSPEND_LINE 0x3d0
127 #define MIPI_DSI_TOP_SUSPEND_PIX 0x3d4
128 #define MIPI_DSI_TOP_MEAS_CNTL 0x3d8
129 /* [0] R stat_edpihalt: edpihalt signal from IP. Default 0. */
130 #define MIPI_DSI_TOP_STAT 0x3dc
131 #define MIPI_DSI_TOP_MEAS_STAT_TE0 0x3e0
132 #define MIPI_DSI_TOP_MEAS_STAT_TE1 0x3e4
133 #define MIPI_DSI_TOP_MEAS_STAT_VS0 0x3e8
134 #define MIPI_DSI_TOP_MEAS_STAT_VS1 0x3ec
135 /* [31:16] RW intr_stat/clr. Default 0.
145 * [15: 0] RW intr_enable. Default 0.
146 * For each bit, 1=enable this interrupt, 0=disable.
153 * [ 0] dwc_edpite interrupt
155 #define MIPI_DSI_TOP_INTR_CNTL_STAT 0x3f0
156 // 31: 2 Reserved. Default 0.
157 // 1: 0 RW mem_pd. Default 3.
158 #define MIPI_DSI_TOP_MEM_PD 0x3f4