Lines Matching +full:audio +full:- +full:bridge
1 // SPDX-License-Identifier: GPL-2.0
57 [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
62 regmap_write(hdmi->regs, TOP_INT_ENABLE00, 0); in mtk_hdmi_v2_hwirq_disable()
63 regmap_write(hdmi->regs, TOP_INT_ENABLE01, 0); in mtk_hdmi_v2_hwirq_disable()
69 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_enable_hpd_pord_irq()
71 regmap_clear_bits(hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_enable_hpd_pord_irq()
77 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); in mtk_hdmi_v2_set_sw_hpd()
78 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_set_sw_hpd()
79 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_set_sw_hpd()
81 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_set_sw_hpd()
82 regmap_clear_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_set_sw_hpd()
83 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD); in mtk_hdmi_v2_set_sw_hpd()
89 struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc; in mtk_hdmi_v2_enable_scrambling()
92 regmap_set_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); in mtk_hdmi_v2_enable_scrambling()
94 regmap_clear_bits(hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON); in mtk_hdmi_v2_enable_scrambling()
96 if (scdc->supported) { in mtk_hdmi_v2_enable_scrambling()
97 if (scdc->scrambling.supported) in mtk_hdmi_v2_enable_scrambling()
98 drm_scdc_set_scrambling(hdmi->curr_conn, enable); in mtk_hdmi_v2_enable_scrambling()
99 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, enable); in mtk_hdmi_v2_enable_scrambling()
107 regmap_set_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); in mtk_hdmi_v2_hw_vid_mute()
109 regmap_clear_bits(hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN); in mtk_hdmi_v2_hw_vid_mute()
117 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN); in mtk_hdmi_v2_hw_aud_mute()
121 regmap_read(hdmi->regs, AIP_CTRL, &aip); in mtk_hdmi_v2_hw_aud_mute()
127 regmap_update_bits(hdmi->regs, AIP_TXCTRL, val, val); in mtk_hdmi_v2_hw_aud_mute()
132 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); in mtk_hdmi_v2_hw_reset()
134 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB); in mtk_hdmi_v2_hw_reset()
150 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); in mtk_hdmi_v2_hw_write_audio_infoframe()
151 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hw_write_audio_infoframe()
153 regmap_write(hdmi->regs, TOP_AIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_audio_infoframe()
154 regmap_write(hdmi->regs, TOP_AIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 3)); in mtk_hdmi_v2_hw_write_audio_infoframe()
155 regmap_write(hdmi->regs, TOP_AIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); in mtk_hdmi_v2_hw_write_audio_infoframe()
156 regmap_write(hdmi->regs, TOP_AIF_PKT02, 0); in mtk_hdmi_v2_hw_write_audio_infoframe()
157 regmap_write(hdmi->regs, TOP_AIF_PKT03, 0); in mtk_hdmi_v2_hw_write_audio_infoframe()
159 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hw_write_audio_infoframe()
160 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR); in mtk_hdmi_v2_hw_write_audio_infoframe()
165 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
166 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
168 regmap_write(hdmi->regs, TOP_AVI_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
169 regmap_write(hdmi->regs, TOP_AVI_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_avi_infoframe()
170 regmap_write(hdmi->regs, TOP_AVI_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
171 regmap_write(hdmi->regs, TOP_AVI_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); in mtk_hdmi_v2_hw_write_avi_infoframe()
172 regmap_write(hdmi->regs, TOP_AVI_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); in mtk_hdmi_v2_hw_write_avi_infoframe()
173 regmap_write(hdmi->regs, TOP_AVI_PKT04, 0); in mtk_hdmi_v2_hw_write_avi_infoframe()
174 regmap_write(hdmi->regs, TOP_AVI_PKT05, 0); in mtk_hdmi_v2_hw_write_avi_infoframe()
176 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
177 regmap_set_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hw_write_avi_infoframe()
182 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
183 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
185 regmap_write(hdmi->regs, TOP_SPDIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
186 regmap_write(hdmi->regs, TOP_SPDIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
187 regmap_write(hdmi->regs, TOP_SPDIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
188 regmap_write(hdmi->regs, TOP_SPDIF_PKT02, mtk_hdmi_v2_format_hw_packet(&buffer[10], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
189 regmap_write(hdmi->regs, TOP_SPDIF_PKT03, mtk_hdmi_v2_format_hw_packet(&buffer[14], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
190 regmap_write(hdmi->regs, TOP_SPDIF_PKT04, mtk_hdmi_v2_format_hw_packet(&buffer[17], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
191 regmap_write(hdmi->regs, TOP_SPDIF_PKT05, mtk_hdmi_v2_format_hw_packet(&buffer[21], 3)); in mtk_hdmi_v2_hw_write_spd_infoframe()
192 regmap_write(hdmi->regs, TOP_SPDIF_PKT06, mtk_hdmi_v2_format_hw_packet(&buffer[24], 4)); in mtk_hdmi_v2_hw_write_spd_infoframe()
193 regmap_write(hdmi->regs, TOP_SPDIF_PKT07, buffer[28]); in mtk_hdmi_v2_hw_write_spd_infoframe()
195 regmap_set_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
196 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hw_write_spd_infoframe()
201 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
202 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
204 regmap_write(hdmi->regs, TOP_VSIF_HEADER, mtk_hdmi_v2_format_hw_packet(&buffer[0], 3)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
205 regmap_write(hdmi->regs, TOP_VSIF_PKT00, mtk_hdmi_v2_format_hw_packet(&buffer[3], 4)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
206 regmap_write(hdmi->regs, TOP_VSIF_PKT01, mtk_hdmi_v2_format_hw_packet(&buffer[7], 2)); in mtk_hdmi_v2_hw_write_vendor_infoframe()
207 regmap_write(hdmi->regs, TOP_VSIF_PKT02, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
208 regmap_write(hdmi->regs, TOP_VSIF_PKT03, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
209 regmap_write(hdmi->regs, TOP_VSIF_PKT04, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
210 regmap_write(hdmi->regs, TOP_VSIF_PKT05, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
211 regmap_write(hdmi->regs, TOP_VSIF_PKT06, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
212 regmap_write(hdmi->regs, TOP_VSIF_PKT07, 0); in mtk_hdmi_v2_hw_write_vendor_infoframe()
214 regmap_set_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
215 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hw_write_vendor_infoframe()
222 regmap_read(hdmi->regs, VID_DOWNSAMPLE_CONFIG, &val); in mtk_hdmi_yuv420_downsampling()
225 regmap_set_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); in mtk_hdmi_yuv420_downsampling()
230 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); in mtk_hdmi_yuv420_downsampling()
232 regmap_set_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); in mtk_hdmi_yuv420_downsampling()
234 regmap_clear_bits(hdmi->regs, hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE); in mtk_hdmi_yuv420_downsampling()
239 regmap_write(hdmi->regs, VID_DOWNSAMPLE_CONFIG, val); in mtk_hdmi_yuv420_downsampling()
241 regmap_clear_bits(hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE); in mtk_hdmi_yuv420_downsampling()
247 struct hdmi_codec_params *params = &hdmi->aud_param.codec_params; in mtk_hdmi_v2_setup_audio_infoframe()
252 memcpy(&frame, ¶ms->cea, sizeof(frame)); in mtk_hdmi_v2_setup_audio_infoframe()
267 regmap_read(hdmi->regs, TOP_CFG01, &val); in mtk_hdmi_v2_hw_gcp_avmute()
277 regmap_write(hdmi->regs, TOP_CFG01, val); in mtk_hdmi_v2_hw_gcp_avmute()
279 regmap_set_bits(hdmi->regs, TOP_INFO_RPT, CP_RPT_EN); in mtk_hdmi_v2_hw_gcp_avmute()
280 regmap_set_bits(hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR); in mtk_hdmi_v2_hw_gcp_avmute()
286 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); in mtk_hdmi_v2_hw_ncts_enable()
288 regmap_clear_bits(hdmi->regs, AIP_CTRL, CTS_SW_SEL); in mtk_hdmi_v2_hw_ncts_enable()
293 u8 *ch_status = hdmi->aud_param.codec_params.iec.status; in mtk_hdmi_v2_hw_aud_set_channel_status()
296 regmap_write(hdmi->regs, AIP_I2S_CHST0, mtk_hdmi_v2_format_hw_packet(&ch_status[0], 4)); in mtk_hdmi_v2_hw_aud_set_channel_status()
297 regmap_write(hdmi->regs, AIP_I2S_CHST1, mtk_hdmi_v2_format_hw_packet(&ch_status[4], 3)); in mtk_hdmi_v2_hw_aud_set_channel_status()
308 regmap_write(hdmi->regs, AIP_N_VAL, n); in mtk_hdmi_v2_hw_aud_set_ncts()
309 regmap_write(hdmi->regs, AIP_CTS_SVAL, cts); in mtk_hdmi_v2_hw_aud_set_ncts()
315 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); in mtk_hdmi_v2_hw_aud_enable()
317 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP); in mtk_hdmi_v2_hw_aud_enable()
326 * Each of the Output Channels (0-7) can be mapped to get their input in mtk_hdmi_v2_aud_output_channel_map()
327 * from any of the available Input Channels (0-7): this function in mtk_hdmi_v2_aud_output_channel_map()
344 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN); in mtk_hdmi_audio_dsd_config()
345 regmap_set_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN); in mtk_hdmi_audio_dsd_config()
352 regmap_write(hdmi->regs, TOP_AUD_MAP, channel_map); in mtk_hdmi_audio_dsd_config()
353 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); in mtk_hdmi_audio_dsd_config()
358 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, in mtk_hdmi_v2_hw_i2s_fifo_map()
364 regmap_update_bits(hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum)); in mtk_hdmi_v2_hw_i2s_ch_number()
402 * Set HDMI Audio packet layout indicator: in mtk_hdmi_v2_hw_i2s_ch_mapping()
407 regmap_set_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); in mtk_hdmi_v2_hw_i2s_ch_mapping()
409 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1); in mtk_hdmi_v2_hw_i2s_ch_mapping()
416 regmap_read(hdmi->regs, AIP_I2S_CTRL, &val); in mtk_hdmi_i2s_data_fmt()
434 regmap_write(hdmi->regs, AIP_I2S_CTRL, val); in mtk_hdmi_i2s_data_fmt()
440 regmap_set_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); in mtk_hdmi_i2s_sck_edge_rise()
442 regmap_clear_bits(hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE); in mtk_hdmi_i2s_sck_edge_rise()
447 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, cbit); in mtk_hdmi_i2s_cbit_order()
453 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, vbit); in mtk_hdmi_i2s_vbit()
458 regmap_update_bits(hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, is_lsb); in mtk_hdmi_i2s_data_direction()
463 regmap_update_bits(hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s)); in mtk_hdmi_v2_hw_audio_type()
539 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, in mtk_hdmi_v2_hw_i2s_ch_swap()
548 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, HBRA_ON); in mtk_hdmi_hbr_config()
549 regmap_set_bits(hdmi->regs, AIP_CTRL, I2S_EN); in mtk_hdmi_hbr_config()
551 regmap_update_bits(hdmi->regs, AIP_CTRL, hbr_mask, SPDIF_EN); in mtk_hdmi_hbr_config()
552 regmap_set_bits(hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE); in mtk_hdmi_hbr_config()
553 regmap_set_bits(hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF); in mtk_hdmi_hbr_config()
554 regmap_set_bits(hdmi->regs, AIP_CTRL, CTS_CAL_N4); in mtk_hdmi_hbr_config()
560 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK); in mtk_hdmi_v2_hw_spdif_config()
561 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE); in mtk_hdmi_v2_hw_spdif_config()
562 regmap_clear_bits(hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK); in mtk_hdmi_v2_hw_spdif_config()
564 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE, in mtk_hdmi_v2_hw_spdif_config()
566 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE, in mtk_hdmi_v2_hw_spdif_config()
568 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH, in mtk_hdmi_v2_hw_spdif_config()
571 regmap_set_bits(hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN); in mtk_hdmi_v2_hw_spdif_config()
576 struct hdmi_audio_param *aud_param = &hdmi->aud_param; in mtk_hdmi_v2_aud_set_input()
577 struct hdmi_codec_params *codec_params = &aud_param->codec_params; in mtk_hdmi_v2_aud_set_input()
583 regmap_write(hdmi->regs, TOP_AUD_MAP, out_ch_map); in mtk_hdmi_v2_aud_set_input()
585 regmap_update_bits(hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, 0); in mtk_hdmi_v2_aud_set_input()
586 regmap_clear_bits(hdmi->regs, AIP_CTRL, in mtk_hdmi_v2_aud_set_input()
589 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1); in mtk_hdmi_v2_aud_set_input()
591 if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) { in mtk_hdmi_v2_aud_set_input()
592 switch (aud_param->aud_codec) { in mtk_hdmi_v2_aud_set_input()
595 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); in mtk_hdmi_v2_aud_set_input()
599 mtk_hdmi_audio_dsd_config(hdmi, codec_params->channels, 0); in mtk_hdmi_v2_aud_set_input()
600 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, 1); in mtk_hdmi_v2_aud_set_input()
603 mtk_hdmi_i2s_data_fmt(hdmi, aud_param->aud_i2s_fmt); in mtk_hdmi_v2_aud_set_input()
610 aud_param->aud_input_chan_type); in mtk_hdmi_v2_aud_set_input()
611 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, codec_params->channels, i2s_ch_map); in mtk_hdmi_v2_aud_set_input()
615 if (codec_params->sample_rate == 768000 && in mtk_hdmi_v2_aud_set_input()
616 (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD || in mtk_hdmi_v2_aud_set_input()
617 aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) { in mtk_hdmi_v2_aud_set_input()
629 regmap_set_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); in mtk_hdmi_v2_hw_audio_input_enable()
631 regmap_clear_bits(hdmi->regs, AIP_CTRL, AUD_IN_EN); in mtk_hdmi_v2_hw_audio_input_enable()
636 regmap_set_bits(hdmi->regs, AIP_CTRL, in mtk_hdmi_v2_aip_ctrl_init()
638 regmap_clear_bits(hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN); in mtk_hdmi_v2_aip_ctrl_init()
646 regmap_set_bits(hdmi->regs, AIP_TXCTRL, arst_bits); in mtk_hdmi_v2_audio_reset()
648 regmap_clear_bits(hdmi->regs, AIP_TXCTRL, arst_bits); in mtk_hdmi_v2_audio_reset()
654 /* Shut down and reset the HDMI Audio HW to avoid glitching */ in mtk_hdmi_v2_aud_output_config()
669 mtk_hdmi_v2_hw_aud_set_ncts(hdmi, hdmi->aud_param.codec_params.sample_rate, in mtk_hdmi_v2_aud_output_config()
670 display_mode->clock); in mtk_hdmi_v2_aud_output_config()
688 regmap_write(hdmi->regs, HDCP_TOP_CTRL, 0); in mtk_hdmi_v2_change_video_resolution()
694 regmap_set_bits(hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT); in mtk_hdmi_v2_change_video_resolution()
700 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR); in mtk_hdmi_v2_change_video_resolution()
701 regmap_set_bits(hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW); in mtk_hdmi_v2_change_video_resolution()
704 regmap_update_bits(hdmi->regs, TOP_CFG00, TMDS_PACK_MODE, in mtk_hdmi_v2_change_video_resolution()
707 regmap_clear_bits(hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN); in mtk_hdmi_v2_change_video_resolution()
709 regmap_clear_bits(hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD); in mtk_hdmi_v2_change_video_resolution()
711 if (hdmi->curr_conn->display_info.is_hdmi) in mtk_hdmi_v2_change_video_resolution()
712 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); in mtk_hdmi_v2_change_video_resolution()
714 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI); in mtk_hdmi_v2_change_video_resolution()
721 regmap_update_bits(hdmi->regs, TOP_CFG01, in mtk_hdmi_v2_change_video_resolution()
726 mtk_hdmi_v2_enable_scrambling(hdmi, hdmi->mode.clock >= 340 * KILO); in mtk_hdmi_v2_change_video_resolution()
728 switch (conn_state->hdmi.output_format) { in mtk_hdmi_v2_change_video_resolution()
743 regmap_set_bits(hdmi->regs, VID_DOWNSAMPLE_CONFIG, in mtk_hdmi_v2_change_video_resolution()
757 .dp = { .link_rate = hdmi->mode.clock * KILO } in mtk_hdmi_v2_output_set_display_mode()
761 ret = phy_configure(hdmi->phy, &opts); in mtk_hdmi_v2_output_set_display_mode()
763 dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret); in mtk_hdmi_v2_output_set_display_mode()
773 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_enable()
777 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_enable()
781 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_enable()
785 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); in mtk_hdmi_v2_clk_enable()
792 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_enable()
794 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_enable()
796 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_enable()
803 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]); in mtk_hdmi_v2_clk_disable()
804 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]); in mtk_hdmi_v2_clk_disable()
805 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]); in mtk_hdmi_v2_clk_disable()
806 clk_disable_unprepare(hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]); in mtk_hdmi_v2_clk_disable()
814 regmap_read(hdmi->regs, HPD_DDC_STATUS, &hpd_status); in mtk_hdmi_v2_hpd_pord_status()
821 * the HDMI spec for reading EDID and for HDMI Audio registers to in mtk_hdmi_v2_hpd_pord_status()
847 regmap_read(hdmi->regs, TOP_INT_STA00, &irq_sta); in mtk_hdmi_v2_isr()
859 regmap_write(hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS); in mtk_hdmi_v2_isr()
860 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); in mtk_hdmi_v2_isr()
871 if (hpd != hdmi->hpd) { in __mtk_hdmi_v2_isr_thread()
872 struct drm_encoder *encoder = hdmi->bridge.encoder; in __mtk_hdmi_v2_isr_thread()
874 hdmi->hpd = hpd; in __mtk_hdmi_v2_isr_thread()
876 if (encoder && encoder->dev) in __mtk_hdmi_v2_isr_thread()
877 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev); in __mtk_hdmi_v2_isr_thread()
899 bool was_active = pm_runtime_active(hdmi->dev); in mtk_hdmi_v2_enable()
902 ret = pm_runtime_resume_and_get(hdmi->dev); in mtk_hdmi_v2_enable()
904 dev_err(hdmi->dev, "Cannot resume HDMI\n"); in mtk_hdmi_v2_enable()
910 pm_runtime_put(hdmi->dev); in mtk_hdmi_v2_enable()
925 pm_runtime_put_sync(hdmi->dev); in mtk_hdmi_v2_disable()
929 * Bridge callbacks
932 static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_attach() argument
936 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_attach()
941 return -EINVAL; in mtk_hdmi_v2_bridge_attach()
943 if (hdmi->next_bridge) { in mtk_hdmi_v2_bridge_attach()
944 ret = drm_bridge_attach(encoder, hdmi->next_bridge, bridge, flags); in mtk_hdmi_v2_bridge_attach()
954 regmap_set_bits(hdmi->regs, HPD_DDC_CTRL, in mtk_hdmi_v2_bridge_attach()
957 irq_clear_status_flags(hdmi->irq, IRQ_NOAUTOEN); in mtk_hdmi_v2_bridge_attach()
958 enable_irq(hdmi->irq); in mtk_hdmi_v2_bridge_attach()
962 * and/or attaching the bridge, without debouncing: if so, we want to in mtk_hdmi_v2_bridge_attach()
974 static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge) in mtk_hdmi_v2_bridge_detach() argument
976 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_detach()
978 WARN_ON(pm_runtime_active(hdmi->dev)); in mtk_hdmi_v2_bridge_detach()
981 disable_irq(hdmi->irq); in mtk_hdmi_v2_bridge_detach()
986 mutex_lock(&hdmi->update_plugged_status_lock); in mtk_hdmi_v2_handle_plugged_change()
987 if (hdmi->plugged_cb && hdmi->codec_dev) in mtk_hdmi_v2_handle_plugged_change()
988 hdmi->plugged_cb(hdmi->codec_dev, plugged); in mtk_hdmi_v2_handle_plugged_change()
989 mutex_unlock(&hdmi->update_plugged_status_lock); in mtk_hdmi_v2_handle_plugged_change()
992 static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_pre_enable() argument
995 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_pre_enable()
998 .dp = { .link_rate = hdmi->mode.clock * KILO } in mtk_hdmi_v2_bridge_pre_enable()
1008 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); in mtk_hdmi_v2_bridge_pre_enable()
1010 conn_state = drm_atomic_get_new_connector_state(state, hdmi->curr_conn); in mtk_hdmi_v2_bridge_pre_enable()
1019 mtk_hdmi_v2_output_set_display_mode(hdmi, conn_state, &hdmi->mode); in mtk_hdmi_v2_bridge_pre_enable()
1022 phy_configure(hdmi->phy, &opts); in mtk_hdmi_v2_bridge_pre_enable()
1025 phy_power_on(hdmi->phy); in mtk_hdmi_v2_bridge_pre_enable()
1027 hdmi->powered = true; in mtk_hdmi_v2_bridge_pre_enable()
1030 static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_enable() argument
1033 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_enable()
1036 if (WARN_ON(!hdmi->powered)) in mtk_hdmi_v2_bridge_enable()
1039 ret = drm_atomic_helper_connector_hdmi_update_infoframes(hdmi->curr_conn, state); in mtk_hdmi_v2_bridge_enable()
1041 dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret); in mtk_hdmi_v2_bridge_enable()
1045 /* signal the connect event to audio codec */ in mtk_hdmi_v2_bridge_enable()
1048 hdmi->enabled = true; in mtk_hdmi_v2_bridge_enable()
1051 static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_disable() argument
1054 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_disable()
1056 if (!hdmi->enabled) in mtk_hdmi_v2_bridge_disable()
1065 hdmi->enabled = false; in mtk_hdmi_v2_bridge_disable()
1068 static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_post_disable() argument
1071 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_post_disable()
1073 if (!hdmi->powered) in mtk_hdmi_v2_bridge_post_disable()
1076 phy_power_off(hdmi->phy); in mtk_hdmi_v2_bridge_post_disable()
1077 hdmi->powered = false; in mtk_hdmi_v2_bridge_post_disable()
1079 /* signal the disconnect event to audio codec */ in mtk_hdmi_v2_bridge_post_disable()
1086 static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_detect() argument
1089 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_bridge_detect()
1091 return hdmi->hpd != HDMI_PLUG_OUT ? in mtk_hdmi_v2_bridge_detect()
1095 static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge, in mtk_hdmi_v2_bridge_edid_read() argument
1101 static void mtk_hdmi_v2_hpd_enable(struct drm_bridge *bridge) in mtk_hdmi_v2_hpd_enable() argument
1103 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hpd_enable()
1108 dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret); in mtk_hdmi_v2_hpd_enable()
1115 static void mtk_hdmi_v2_hpd_disable(struct drm_bridge *bridge) in mtk_hdmi_v2_hpd_disable() argument
1117 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hpd_disable()
1123 static int mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, in mtk_hdmi_v2_hdmi_tmds_char_rate_valid() argument
1127 if (mode->clock < MTK_HDMI_V2_CLOCK_MIN) in mtk_hdmi_v2_hdmi_tmds_char_rate_valid()
1129 else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX) in mtk_hdmi_v2_hdmi_tmds_char_rate_valid()
1135 static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge, in mtk_hdmi_v2_hdmi_clear_infoframe() argument
1138 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hdmi_clear_infoframe()
1142 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1143 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1146 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1147 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1150 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1151 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1154 regmap_clear_bits(hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1155 regmap_clear_bits(hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN); in mtk_hdmi_v2_hdmi_clear_infoframe()
1165 static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge, in mtk_hdmi_v2_hdmi_write_infoframe() argument
1169 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_hdmi_write_infoframe()
1186 dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type); in mtk_hdmi_v2_hdmi_write_infoframe()
1195 struct drm_display_mode *mode = &hdmi->mode; in mtk_hdmi_v2_set_abist()
1196 int abist_format = -EINVAL; in mtk_hdmi_v2_set_abist()
1200 regmap_clear_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); in mtk_hdmi_v2_set_abist()
1204 if (!mode->hdisplay || !mode->vdisplay) in mtk_hdmi_v2_set_abist()
1205 return -EINVAL; in mtk_hdmi_v2_set_abist()
1207 interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; in mtk_hdmi_v2_set_abist()
1209 switch (mode->hdisplay) { in mtk_hdmi_v2_set_abist()
1211 if (mode->vdisplay == 480) in mtk_hdmi_v2_set_abist()
1213 else if (mode->vdisplay == 576) in mtk_hdmi_v2_set_abist()
1217 if (mode->vdisplay == 720) in mtk_hdmi_v2_set_abist()
1221 if (mode->vdisplay == 480) in mtk_hdmi_v2_set_abist()
1223 else if (mode->vdisplay == 576) in mtk_hdmi_v2_set_abist()
1227 if (mode->vdisplay == 1080) in mtk_hdmi_v2_set_abist()
1231 if (mode->vdisplay == 2160) in mtk_hdmi_v2_set_abist()
1235 if (mode->vdisplay == 2160) in mtk_hdmi_v2_set_abist()
1244 regmap_update_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT, in mtk_hdmi_v2_set_abist()
1246 regmap_set_bits(hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE); in mtk_hdmi_v2_set_abist()
1252 struct mtk_hdmi *hdmi = m->private; in mtk_hdmi_v2_debug_abist_show()
1258 return -EINVAL; in mtk_hdmi_v2_debug_abist_show()
1260 ret = regmap_read(hdmi->regs, TOP_CFG00, &val); in mtk_hdmi_v2_debug_abist_show()
1266 seq_printf(m, "HDMI Automated Built-In Self Test: %s\n", in mtk_hdmi_v2_debug_abist_show()
1276 struct seq_file *m = file->private_data; in mtk_hdmi_v2_debug_abist_write()
1280 if (!m || !m->private || *offp) in mtk_hdmi_v2_debug_abist_write()
1281 return -EINVAL; in mtk_hdmi_v2_debug_abist_write()
1288 return -EINVAL; in mtk_hdmi_v2_debug_abist_write()
1290 mtk_hdmi_v2_set_abist((struct mtk_hdmi *)m->private, en); in mtk_hdmi_v2_debug_abist_write()
1296 return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private); in mtk_hdmi_v2_debug_abist_open()
1308 static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root) in mtk_hdmi_v2_debugfs_init() argument
1310 struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(bridge); in mtk_hdmi_v2_debugfs_init()
1338 * HDMI audio codec callbacks
1348 return -ENODEV; in mtk_hdmi_v2_audio_hook_plugged_cb()
1351 plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON); in mtk_hdmi_v2_audio_hook_plugged_cb()
1363 if (hdmi->audio_enable) { in mtk_hdmi_v2_audio_hw_params()
1365 mtk_hdmi_v2_aud_output_config(hdmi, &hdmi->mode); in mtk_hdmi_v2_audio_hw_params()
1375 hdmi->audio_enable = true; in mtk_hdmi_v2_audio_startup()
1384 hdmi->audio_enable = false; in mtk_hdmi_v2_audio_shutdown()
1447 /* Populate HDMI sub-devices if present */ in mtk_hdmi_v2_probe()
1448 ret = devm_of_platform_populate(&pdev->dev); in mtk_hdmi_v2_probe()
1456 hdmi->hpd = HDMI_PLUG_OUT; in mtk_hdmi_v2_probe()
1466 regmap_write(hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0)); in mtk_hdmi_v2_probe()
1467 regmap_write(hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0)); in mtk_hdmi_v2_probe()
1470 regmap_write(hdmi->regs, TOP_INT_CLR00, 0); in mtk_hdmi_v2_probe()
1471 regmap_write(hdmi->regs, TOP_INT_CLR01, 0); in mtk_hdmi_v2_probe()
1478 irq_set_status_flags(hdmi->irq, IRQ_NOAUTOEN); in mtk_hdmi_v2_probe()
1479 ret = devm_request_threaded_irq(&pdev->dev, hdmi->irq, mtk_hdmi_v2_isr, in mtk_hdmi_v2_probe()
1482 dev_name(&pdev->dev), hdmi); in mtk_hdmi_v2_probe()
1484 return dev_err_probe(&pdev->dev, ret, "Cannot request IRQ\n"); in mtk_hdmi_v2_probe()
1486 ret = devm_pm_runtime_enable(&pdev->dev); in mtk_hdmi_v2_probe()
1488 return dev_err_probe(&pdev->dev, ret, "Cannot enable Runtime PM\n"); in mtk_hdmi_v2_probe()
1497 i2c_put_adapter(hdmi->ddc_adpt); in mtk_hdmi_v2_remove()
1501 { .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
1502 { .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
1511 .name = "mediatek-drm-hdmi-v2",