Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
12 #define LR_SWAP BIT(0)
13 #define LFE_CC_SWAP BIT(1)
14 #define LSRS_SWAP BIT(2)
15 #define RLS_RRS_SWAP BIT(3)
16 #define LR_STATUS_SWAP BIT(4)
23 #define I2S_UV_V BIT(0)
24 #define I2S_UV_U BIT(1)
26 #define I2S_UV_CH_EN(x) BIT((x) + 2)
27 #define I2S_UV_TMDS_DEBUG BIT(6)
28 #define I2S_UV_NORMAL_INFO_INV BIT(7)
30 #define VS_EN BIT(0)
31 #define ACP_EN BIT(1)
32 #define ISRC1_EN BIT(2)
33 #define ISRC2_EN BIT(3)
34 #define GAMUT_EN BIT(4)
36 #define CTS_CTRL_SOFT BIT(0)
38 #define INT_MDI BIT(0)
39 #define INT_HDCP BIT(1)
40 #define INT_FIFO_O BIT(2)
41 #define INT_FIFO_U BIT(3)
42 #define INT_IFM_ERR BIT(4)
43 #define INT_INF_DONE BIT(5)
44 #define INT_NCTS_DONE BIT(6)
45 #define INT_CTRL_PKT_DONE BIT(7)
48 #define CTRL_GEN_EN BIT(2)
49 #define CTRL_SPD_EN BIT(3)
50 #define CTRL_MPEG_EN BIT(4)
51 #define CTRL_AUDIO_EN BIT(5)
52 #define CTRL_AVI_EN BIT(6)
53 #define CTRL_AVMUTE BIT(7)
55 #define STATUS_HTPLG BIT(0)
56 #define STATUS_PORD BIT(1)
58 #define NCTS_WRI_ANYTIME BIT(6)
60 #define AUDIO_ZERO BIT(0)
61 #define HIGH_BIT_RATE BIT(1)
62 #define SACD_DST BIT(2)
63 #define DST_NORMAL_DOUBLE BIT(3)
64 #define DSD_INV BIT(4)
65 #define LR_INV BIT(5)
66 #define LR_MIX BIT(6)
67 #define DSD_SEL BIT(7)
77 #define MIX_CTRL_SRC_EN BIT(0)
78 #define BYPASS_VOLUME BIT(1)
79 #define MIX_CTRL_FLAT BIT(7)
85 #define AOUT_FIFO_ADAP_CTRL BIT(6)
86 #define AOUT_BURST_PREAMBLE_EN BIT(7)
91 #define AUDIO_PACKET_OFF BIT(6)
101 #define CFG1_EDG_SEL BIT(0)
102 #define CFG1_SPDIF BIT(1)
103 #define CFG1_DVI BIT(2)
104 #define CFG1_HDCP_DEBUG BIT(3)
106 #define CFG2_MHL_DE_SEL BIT(3)
107 #define CFG2_MHL_FAKE_DE_SEL BIT(4)
108 #define CFG2_MHL_DATA_REMAP BIT(5)
109 #define CFG2_NOTICE_EN BIT(6)
110 #define CFG2_ACLK_INV BIT(7)
113 #define CFG3_CONTROL_PACKET_DELAY BIT(6)
114 #define CFG3_KSV_LOAD_START BIT(7)
116 #define CFG4_AES_KEY_LOAD BIT(4)
117 #define CFG4_AV_UNMUTE_EN BIT(5)
118 #define CFG4_AV_UNMUTE_SET BIT(6)
119 #define CFG4_MHL_MODE BIT(7)
130 #define CHM2_SEL (0x3 << 6)
131 #define AUDIO_I2S_NCTS_SEL BIT(1)
134 #define NEW_GCP_CTRL BIT(0)
135 #define NEW_GCP_CTRL_MERGE BIT(0)
186 #define ABIST_EN BIT(7)
193 #define VIDEO_SOURCE_SEL BIT(7)
198 #define HDMI_ON BIT(0)
199 #define HDMI_RST BIT(1)
200 #define ANLG_ON BIT(2)
201 #define CFG10_DVI BIT(3)
202 #define HDMI_TST BIT(3)
205 #define AUD_OUTSYNC_EN BIT(24)
206 #define AUD_OUTSYNC_PRE_EN BIT(25)
207 #define I2CM_ON BIT(26)
208 #define E2PROM_TYPE_8BIT BIT(27)
209 #define MCM_E2PROM_ON BIT(28)
210 #define EXT_E2PROM_ON BIT(29)
211 #define HTPLG_PIN_SEL_OFF BIT(30)
212 #define AES_EFUSE_ENABLE BIT(31)
219 #define DEEP_COLOR_EN BIT(0)
220 #define HDMI_AUDIO_TEST_SEL BIT(8)
221 #define HDMI2P0_EN BIT(11)
222 #define HDMI_OUT_FIFO_EN BIT(16)
223 #define HDMI_OUT_FIFO_CLK_INV BIT(17)
224 #define MHL_MODE_ON BIT(28)
225 #define MHL_PP_MODE BIT(29)
226 #define MHL_SYNC_AUTO_EN BIT(30)
227 #define HDMI_PCLK_FREE_RUN BIT(31)