1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/arm-smccc.h>
24 #include <sound/hdmi-codec.h>
49 	regmap_update_bits(hdmi->regs, VIDEO_CFG_4,  in mtk_hdmi_hw_vid_black()
63 	if (hdmi->conf && hdmi->conf->tz_disabled)  in mtk_hdmi_hw_make_reg_writable()
64 		regmap_update_bits(hdmi->sys_regmap,  in mtk_hdmi_hw_make_reg_writable()
65 				   hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_make_reg_writable()
71 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_make_reg_writable()
73 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,  in mtk_hdmi_hw_make_reg_writable()
79 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_1p4_version_enable()
85 	regmap_set_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);  in mtk_hdmi_hw_aud_mute()
90 	regmap_clear_bits(hdmi->regs, GRL_AUDIO_CFG, AUDIO_ZERO);  in mtk_hdmi_hw_aud_unmute()
95 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,  in mtk_hdmi_hw_reset()
97 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,  in mtk_hdmi_hw_reset()
99 	regmap_clear_bits(hdmi->regs, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);  in mtk_hdmi_hw_reset()
100 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,  in mtk_hdmi_hw_reset()
106 	regmap_update_bits(hdmi->regs, GRL_CFG2, CFG2_NOTICE_EN,  in mtk_hdmi_hw_enable_notice()
112 	regmap_write(hdmi->regs, GRL_INT_MASK, int_mask);  in mtk_hdmi_hw_write_int_mask()
117 	regmap_update_bits(hdmi->regs, GRL_CFG1, CFG1_DVI, enable ? CFG1_DVI : 0);  in mtk_hdmi_hw_enable_dvi_mode()
138 	dev_dbg(hdmi->dev,  in mtk_hdmi_hw_send_info_frame()
160 		dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);  in mtk_hdmi_hw_send_info_frame()
163 	regmap_clear_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);  in mtk_hdmi_hw_send_info_frame()
164 	regmap_write(hdmi->regs, GRL_INFOFRM_TYPE, frame_type);  in mtk_hdmi_hw_send_info_frame()
165 	regmap_write(hdmi->regs, GRL_INFOFRM_VER, frame_ver);  in mtk_hdmi_hw_send_info_frame()
166 	regmap_write(hdmi->regs, GRL_INFOFRM_LNG, frame_len);  in mtk_hdmi_hw_send_info_frame()
168 	regmap_write(hdmi->regs, GRL_IFM_PORT, checksum);  in mtk_hdmi_hw_send_info_frame()
170 		regmap_write(hdmi->regs, GRL_IFM_PORT, frame_data[i]);  in mtk_hdmi_hw_send_info_frame()
172 	regmap_set_bits(hdmi->regs, ctrl_reg, ctrl_frame_en);  in mtk_hdmi_hw_send_info_frame()
177 	regmap_update_bits(hdmi->regs, GRL_SHIFT_R2,  in mtk_hdmi_hw_send_aud_packet()
183 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_config_sys()
186 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_config_sys()
192 	regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,  in mtk_hdmi_hw_set_deep_color_mode()
199 	regmap_clear_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);  in mtk_hdmi_hw_send_av_mute()
201 	regmap_set_bits(hdmi->regs, GRL_CFG4, CTRL_AVMUTE);  in mtk_hdmi_hw_send_av_mute()
206 	regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,  in mtk_hdmi_hw_send_av_unmute()
209 	regmap_update_bits(hdmi->regs, GRL_CFG4, CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET,  in mtk_hdmi_hw_send_av_unmute()
215 	regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, CTS_CTRL_SOFT,  in mtk_hdmi_hw_ncts_enable()
222 	regmap_update_bits(hdmi->regs, GRL_CTS_CTRL, NCTS_WRI_ANYTIME,  in mtk_hdmi_hw_ncts_auto_write_enable()
229 	regmap_clear_bits(hdmi->regs, GRL_CFG4, CFG4_MHL_MODE);  in mtk_hdmi_hw_msic_setting()
231 	if (mode->flags & DRM_MODE_FLAG_INTERLACE &&  in mtk_hdmi_hw_msic_setting()
232 	    mode->clock == 74250 &&  in mtk_hdmi_hw_msic_setting()
233 	    mode->vdisplay == 1080)  in mtk_hdmi_hw_msic_setting()
234 		regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);  in mtk_hdmi_hw_msic_setting()
236 		regmap_set_bits(hdmi->regs, GRL_CFG2, CFG2_MHL_DE_SEL);  in mtk_hdmi_hw_msic_setting()
264 	regmap_update_bits(hdmi->regs, GRL_CH_SWAP, 0xff, swap_bit);  in mtk_hdmi_hw_aud_set_channel_swap()
285 	regmap_update_bits(hdmi->regs, GRL_AOUT_CFG, AOUT_BNUM_SEL_MASK, val);  in mtk_hdmi_hw_aud_set_bit_num()
293 	regmap_read(hdmi->regs, GRL_CFG0, &val);  in mtk_hdmi_hw_aud_set_i2s_fmt()
317 	regmap_write(hdmi->regs, GRL_CFG0, val);  in mtk_hdmi_hw_aud_set_i2s_fmt()
326 	regmap_clear_bits(hdmi->regs, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);  in mtk_hdmi_hw_audio_config()
333 	regmap_update_bits(hdmi->regs, GRL_AUDIO_CFG, mask, val);  in mtk_hdmi_hw_audio_config()
374 	regmap_write(hdmi->regs, GRL_CH_SW0, ch_switch & 0xff);  in mtk_hdmi_hw_aud_set_i2s_chan_num()
375 	regmap_write(hdmi->regs, GRL_CH_SW1, (ch_switch >> 8) & 0xff);  in mtk_hdmi_hw_aud_set_i2s_chan_num()
376 	regmap_write(hdmi->regs, GRL_CH_SW2, (ch_switch >> 16) & 0xff);  in mtk_hdmi_hw_aud_set_i2s_chan_num()
377 	regmap_write(hdmi->regs, GRL_I2S_UV, i2s_uv);  in mtk_hdmi_hw_aud_set_i2s_chan_num()
385 	regmap_read(hdmi->regs, GRL_CFG1, &val);  in mtk_hdmi_hw_aud_set_input_type()
393 	regmap_write(hdmi->regs, GRL_CFG1, val);  in mtk_hdmi_hw_aud_set_input_type()
402 		regmap_write(hdmi->regs, GRL_I2S_C_STA0 + i * 4, channel_status[i]);  in mtk_hdmi_hw_aud_set_channel_status()
403 		regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, channel_status[i]);  in mtk_hdmi_hw_aud_set_channel_status()
404 		regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, channel_status[i]);  in mtk_hdmi_hw_aud_set_channel_status()
407 		regmap_write(hdmi->regs, GRL_L_STATUS_0 + i * 4, 0);  in mtk_hdmi_hw_aud_set_channel_status()
408 		regmap_write(hdmi->regs, GRL_R_STATUS_0 + i * 4, 0);  in mtk_hdmi_hw_aud_set_channel_status()
416 	regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);  in mtk_hdmi_hw_aud_src_reenable()
419 		regmap_write(hdmi->regs, GRL_MIX_CTRL, val);  in mtk_hdmi_hw_aud_src_reenable()
422 		regmap_write(hdmi->regs, GRL_MIX_CTRL, val);  in mtk_hdmi_hw_aud_src_reenable()
430 	regmap_read(hdmi->regs, GRL_MIX_CTRL, &val);  in mtk_hdmi_hw_aud_src_disable()
432 	regmap_write(hdmi->regs, GRL_MIX_CTRL, val);  in mtk_hdmi_hw_aud_src_disable()
433 	regmap_write(hdmi->regs, GRL_SHIFT_L1, 0x00);  in mtk_hdmi_hw_aud_src_disable()
441 	regmap_read(hdmi->regs, GRL_CFG5, &val);  in mtk_hdmi_hw_aud_set_mclk()
464 	regmap_write(hdmi->regs, GRL_CFG5, val);  in mtk_hdmi_hw_aud_set_mclk()
473 	regmap_write(hdmi->regs, GRL_NCTS, 0);  in do_hdmi_hw_aud_set_ncts()
474 	regmap_write(hdmi->regs, GRL_NCTS, 0);  in do_hdmi_hw_aud_set_ncts()
475 	regmap_write(hdmi->regs, GRL_NCTS, 0);  in do_hdmi_hw_aud_set_ncts()
488 		regmap_write(hdmi->regs, GRL_NCTS, val[i]);  in do_hdmi_hw_aud_set_ncts()
499 	dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",  in mtk_hdmi_hw_aud_set_ncts()
502 	regmap_update_bits(hdmi->regs, DUMMY_304, AUDIO_I2S_NCTS_SEL, AUDIO_I2S_NCTS_SEL_64);  in mtk_hdmi_hw_aud_set_ncts()
582 	ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);  in mtk_hdmi_video_change_vpll()
584 		dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,  in mtk_hdmi_video_change_vpll()
589 	rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);  in mtk_hdmi_video_change_vpll()
592 		dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,  in mtk_hdmi_video_change_vpll()
595 		dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);  in mtk_hdmi_video_change_vpll()
608 	mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);  in mtk_hdmi_video_set_display_mode()
622 	regmap_set_bits(hdmi->regs, GRL_MIX_CTRL, MIX_CTRL_FLAT);  in mtk_hdmi_aud_set_input()
624 	if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&  in mtk_hdmi_aud_set_input()
625 	    hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {  in mtk_hdmi_aud_set_input()
627 	} else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {  in mtk_hdmi_aud_set_input()
628 		hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;  in mtk_hdmi_aud_set_input()
631 	mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);  in mtk_hdmi_aud_set_input()
634 	dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&  in mtk_hdmi_aud_set_input()
635 	       (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));  in mtk_hdmi_aud_set_input()
638 	if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)  in mtk_hdmi_aud_set_input()
641 		chan_type = hdmi->aud_param.aud_input_chan_type;  in mtk_hdmi_aud_set_input()
644 	mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);  in mtk_hdmi_aud_set_input()
650 	unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;  in mtk_hdmi_aud_set_src()
654 	regmap_clear_bits(hdmi->regs, GRL_CFG2, CFG2_ACLK_INV);  in mtk_hdmi_aud_set_src()
656 	if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {  in mtk_hdmi_aud_set_src()
665 			return -EINVAL;  in mtk_hdmi_aud_set_src()
667 		mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);  in mtk_hdmi_aud_set_src()
675 			return -EINVAL;  in mtk_hdmi_aud_set_src()
680 	mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);  in mtk_hdmi_aud_set_src()
695 			hdmi->aud_param.codec_params.iec.status);  in mtk_hdmi_aud_output_config()
713 						       hdmi->curr_conn, mode);  in mtk_hdmi_setup_avi_infoframe()
715 		dev_err(hdmi->dev,  in mtk_hdmi_setup_avi_infoframe()
722 		dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);  in mtk_hdmi_setup_avi_infoframe()
732 	struct drm_bridge *bridge = &hdmi->bridge;  in mtk_hdmi_setup_spd_infoframe()  local
737 	err = hdmi_spd_infoframe_init(&frame, bridge->vendor, bridge->product);  in mtk_hdmi_setup_spd_infoframe()
739 		dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",  in mtk_hdmi_setup_spd_infoframe()
746 		dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);  in mtk_hdmi_setup_spd_infoframe()
762 		dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",  in mtk_hdmi_setup_audio_infoframe()
771 					hdmi->aud_param.aud_input_chan_type);  in mtk_hdmi_setup_audio_infoframe()
775 		dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",  in mtk_hdmi_setup_audio_infoframe()
792 							  hdmi->curr_conn, mode);  in mtk_hdmi_setup_vendor_specific_infoframe()
794 		dev_err(hdmi->dev,  in mtk_hdmi_setup_vendor_specific_infoframe()
801 		dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",  in mtk_hdmi_setup_vendor_specific_infoframe()
813 	hdmi->audio_enable = true;  in mtk_hdmi_audio_enable()
819 	hdmi->audio_enable = false;  in mtk_hdmi_audio_disable()
830 	phy_power_off(hdmi->phy);  in mtk_hdmi_output_set_display_mode()
833 					 mode->clock * 1000);  in mtk_hdmi_output_set_display_mode()
835 		dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);  in mtk_hdmi_output_set_display_mode()
840 	phy_power_on(hdmi->phy);  in mtk_hdmi_output_set_display_mode()
861 	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);  in mtk_hdmi_clk_enable_audio()
865 	ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);  in mtk_hdmi_clk_enable_audio()
867 		clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);  in mtk_hdmi_clk_enable_audio()
876 	clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);  in mtk_hdmi_clk_disable_audio()
877 	clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);  in mtk_hdmi_clk_disable_audio()
885 	mutex_lock(&hdmi->update_plugged_status_lock);  in mtk_hdmi_update_plugged_status()
886 	connected = mtk_cec_hpd_high(hdmi->cec_dev);  in mtk_hdmi_update_plugged_status()
887 	if (hdmi->plugged_cb && hdmi->codec_dev)  in mtk_hdmi_update_plugged_status()
888 		hdmi->plugged_cb(hdmi->codec_dev, connected);  in mtk_hdmi_update_plugged_status()
889 	mutex_unlock(&hdmi->update_plugged_status_lock);  in mtk_hdmi_update_plugged_status()
901 mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,  in mtk_hdmi_bridge_mode_valid()  argument
905 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_mode_valid()
907 	dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",  in mtk_hdmi_bridge_mode_valid()
908 		mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),  in mtk_hdmi_bridge_mode_valid()
909 		!!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);  in mtk_hdmi_bridge_mode_valid()
911 	if (hdmi->conf) {  in mtk_hdmi_bridge_mode_valid()
912 		if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))  in mtk_hdmi_bridge_mode_valid()
915 		if (hdmi->conf->max_mode_clock &&  in mtk_hdmi_bridge_mode_valid()
916 		    mode->clock > hdmi->conf->max_mode_clock)  in mtk_hdmi_bridge_mode_valid()
920 	if (mode->clock < 27000)  in mtk_hdmi_bridge_mode_valid()
922 	if (mode->clock > 297000)  in mtk_hdmi_bridge_mode_valid()
932 	if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {  in mtk_hdmi_hpd_event()
936 		drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);  in mtk_hdmi_hpd_event()
937 		drm_bridge_hpd_notify(&hdmi->bridge, status);  in mtk_hdmi_hpd_event()
942  * Bridge callbacks
946 mtk_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)  in mtk_hdmi_bridge_detect()  argument
948 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_detect()
953 static const struct drm_edid *mtk_hdmi_bridge_edid_read(struct drm_bridge *bridge,  in mtk_hdmi_bridge_edid_read()  argument
956 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_edid_read()
959 	if (!hdmi->ddc_adpt)  in mtk_hdmi_bridge_edid_read()
961 	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_adpt);  in mtk_hdmi_bridge_edid_read()
964 		 * FIXME: This should use !connector->display_info.has_audio (or  in mtk_hdmi_bridge_edid_read()
965 		 * !connector->display_info.is_hdmi) from a path that has read  in mtk_hdmi_bridge_edid_read()
970 		hdmi->dvi_mode = !drm_detect_monitor_audio(edid);  in mtk_hdmi_bridge_edid_read()
976 static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,  in mtk_hdmi_bridge_attach()  argument
980 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_attach()
986 		return -EINVAL;  in mtk_hdmi_bridge_attach()
989 	if (hdmi->next_bridge) {  in mtk_hdmi_bridge_attach()
990 		ret = drm_bridge_attach(encoder, hdmi->next_bridge,  in mtk_hdmi_bridge_attach()
991 					bridge, flags);  in mtk_hdmi_bridge_attach()
996 	mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);  in mtk_hdmi_bridge_attach()
1001 static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,  in mtk_hdmi_bridge_atomic_disable()  argument
1004 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_atomic_disable()
1006 	if (!hdmi->enabled)  in mtk_hdmi_bridge_atomic_disable()
1009 	phy_power_off(hdmi->phy);  in mtk_hdmi_bridge_atomic_disable()
1010 	clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);  in mtk_hdmi_bridge_atomic_disable()
1011 	clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);  in mtk_hdmi_bridge_atomic_disable()
1013 	hdmi->curr_conn = NULL;  in mtk_hdmi_bridge_atomic_disable()
1015 	hdmi->enabled = false;  in mtk_hdmi_bridge_atomic_disable()
1018 static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,  in mtk_hdmi_bridge_atomic_post_disable()  argument
1021 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_atomic_post_disable()
1023 	if (!hdmi->powered)  in mtk_hdmi_bridge_atomic_post_disable()
1029 	hdmi->powered = false;  in mtk_hdmi_bridge_atomic_post_disable()
1032 static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,  in mtk_hdmi_bridge_atomic_pre_enable()  argument
1035 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_atomic_pre_enable()
1040 	hdmi->powered = true;  in mtk_hdmi_bridge_atomic_pre_enable()
1049 	if (mode->flags & DRM_MODE_FLAG_3D_MASK)  in mtk_hdmi_send_infoframe()
1053 static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,  in mtk_hdmi_bridge_atomic_enable()  argument
1056 	struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);  in mtk_hdmi_bridge_atomic_enable()
1059 	hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,  in mtk_hdmi_bridge_atomic_enable()
1060 								   bridge->encoder);  in mtk_hdmi_bridge_atomic_enable()
1062 	mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);  in mtk_hdmi_bridge_atomic_enable()
1063 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);  in mtk_hdmi_bridge_atomic_enable()
1064 	clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);  in mtk_hdmi_bridge_atomic_enable()
1065 	phy_power_on(hdmi->phy);  in mtk_hdmi_bridge_atomic_enable()
1066 	mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);  in mtk_hdmi_bridge_atomic_enable()
1068 	hdmi->enabled = true;  in mtk_hdmi_bridge_atomic_enable()
1088  * HDMI audio codec callbacks
1097 	if (!hdmi->audio_enable) {  in mtk_hdmi_audio_hw_params()
1098 		dev_err(hdmi->dev, "hdmi audio is in disable state!\n");  in mtk_hdmi_audio_hw_params()
1099 		return -EINVAL;  in mtk_hdmi_audio_hw_params()
1103 	mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);  in mtk_hdmi_audio_hw_params()
1168 	if (!hdmi->cec_dev)  in mtk_hdmi_probe()
1169 		return dev_err_probe(hdmi->dev, -ENODEV, "CEC is required by HDMIv1\n");  in mtk_hdmi_probe()
1173 		return dev_err_probe(hdmi->dev, ret,  in mtk_hdmi_probe()
1174 				     "Failed to enable audio clocks\n");  in mtk_hdmi_probe()
1227 	{ .compatible = "mediatek,mt2701-hdmi", .data = &mtk_hdmi_conf_mt2701 },
1228 	{ .compatible = "mediatek,mt8167-hdmi", .data = &mtk_hdmi_conf_mt8167 },
1229 	{ .compatible = "mediatek,mt8173-hdmi", .data = &mtk_hdmi_conf_mt8173 },
1238 		.name = "mediatek-drm-hdmi",