Lines Matching +full:15 +full:- +full:9

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (c) 2019-2022 MediaTek Inc.
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL		BIT(15)
27 #define DA_CKM_XTAL_CK_FORCE_VAL		BIT(9)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS		GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS		GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS		GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS		GENMASK(15, 12)
65 #define DP_TX1_VOLT_SWING_MASK			GENMASK(9, 8)
88 #define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)
90 #define HTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
92 #define VTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
94 #define HSTART_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
96 #define VSTART_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
98 #define HWIDTH_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
100 #define VHEIGHT_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)
103 #define HSP_SW_DP_ENC0_P0_MASK				BIT(15)
106 #define VSP_SW_DP_ENC0_P0_MASK				BIT(15)
117 #define VSW_SEL_DP_ENC0_P0				BIT(9)
135 #define VIDEO_MN_GEN_EN_DP_ENC0_P0			BIT(15)
143 #define HDE_NUM_LAST_DP_ENC0_P0_MASK			GENMASK(15, 0)
149 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK			BIT(15)
151 #define CH_STATUS_0_DP_ENC0_P0_MASK			GENMASK(15, 0)
153 #define CH_STATUS_1_DP_ENC0_P0_MASK			GENMASK(15, 0)
177 #define ASP_HB3_DP_ENC0_P0_MASK				GENMASK(15, 8)
203 #define ISRC1_HB3_DP_ENC0_P0_MASK			GENMASK(15, 8)
213 #define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK		GENMASK(9, 8)
216 #define AU_CH_STS_REGEN_DP_ENC1_P0_MASK			BIT(9)
219 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK		GENMASK(9, 8)
225 #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK		GENMASK(15, 12)
244 #define DP_ENC_DUMMY_RW_1				BIT(9)
251 #define PATTERN4_EN_DP_TRANS_P0_MASK				BIT(15)
262 #define HPD_CONN_THD_DP_TRANS_P0_MASK				GENMASK(15, 12)
271 #define IRQ_STATUS_DP_TRANS_P0_MASK				GENMASK(15, 12)
285 #define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK		BIT(9)
289 #define SW_IRQ_CLR_DP_TRANS_P0_MASK				GENMASK(15, 0)
290 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK				GENMASK(15, 0)
292 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK			GENMASK(15, 0)
305 #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK			BIT(9)
308 #define AUX_RD_MODE_AUX_TX_P0_MASK			BIT(9)
314 #define AUX_RX_PHY_STATE_AUX_TX_P0_MASK			GENMASK(9, 0)
319 #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK		GENMASK(15, 2)
323 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK		GENMASK(15, 8)
343 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK		GENMASK(15, 0)
347 #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK			GENMASK(15, 12)
348 #define PHY_FIFO_RST_AUX_TX_P0_MASK			BIT(9)