Lines Matching +full:1 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
35 #define DA_XTP_GLB_LDO_EN_FORCE_VAL BIT(1)
38 #define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
41 #define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
44 #define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
47 #define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
51 #define RG_XTP_GLB_CKDET_EN BIT(1)
56 #define DP_PWR_STATE_MASK GENMASK(1, 0)
58 #define DP_PWR_STATE_BANDGAP_TPLL BIT(1)
59 #define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)
61 #define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)
82 #define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)
91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
93 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
95 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
97 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
99 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
101 #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
104 #define HSP_SW_DP_ENC0_P0_MASK BIT(15)
107 #define VSP_SW_DP_ENC0_P0_MASK BIT(15)
110 #define VTOTAL_SEL_DP_ENC0_P0 BIT(1)
128 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT (1 << 8)
134 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << 12)
136 #define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)
144 #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
150 #define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)
152 #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
154 #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
163 #define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
169 #define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
178 #define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
204 #define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
226 #define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)
233 #define BS2BS_MODE_DP_ENC1_P0_VAL 1
252 #define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)
263 #define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)
269 #define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << 4)
272 #define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)
277 #define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)
278 #define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)
290 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
291 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
293 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
319 #define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK BIT(1)
320 #define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)
324 #define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)
332 #define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0 BIT(1)
344 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
348 #define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)
356 #define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1)