Lines Matching +full:0 +full:x3600
9 #define SEC_OFFSET 0x4000
15 /* offset: 0x0 */
16 #define DP_PHY_GLB_BIAS_GEN_00 0x0
18 #define DP_PHY_GLB_DPAUX_TX 0x8
20 #define MTK_DP_0034 0x34
36 #define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
37 #define DP_PHY_LANE_TX_0 0x104
40 #define DP_PHY_LANE_TX_1 0x204
43 #define DP_PHY_LANE_TX_2 0x304
46 #define DP_PHY_LANE_TX_3 0x404
49 #define MTK_DP_1040 0x1040
52 #define RG_DPAUX_RX_EN BIT(0)
54 /* offset: TOP_OFFSET (0x2000) */
55 #define MTK_DP_TOP_PWR_STATE 0x2000
56 #define DP_PWR_STATE_MASK GENMASK(1, 0)
57 #define DP_PWR_STATE_BANDGAP BIT(0)
59 #define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)
60 #define MTK_DP_TOP_SWING_EMP 0x2004
61 #define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)
62 #define DP_TX0_VOLT_SWING_SHIFT 0
72 #define MTK_DP_TOP_RESET_AND_PROBE 0x2020
74 #define MTK_DP_TOP_IRQ_MASK 0x202c
76 #define MTK_DP_TOP_MEM_PD 0x2038
77 #define MEM_ISO_EN BIT(0)
80 /* offset: ENC0_OFFSET (0x3000) */
81 #define MTK_DP_ENC0_P0_3000 0x3000
82 #define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)
86 #define MTK_DP_ENC0_P0_3004 0x3004
90 #define MTK_DP_ENC0_P0_3010 0x3010
91 #define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
92 #define MTK_DP_ENC0_P0_3014 0x3014
93 #define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
94 #define MTK_DP_ENC0_P0_3018 0x3018
95 #define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
96 #define MTK_DP_ENC0_P0_301C 0x301c
97 #define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
98 #define MTK_DP_ENC0_P0_3020 0x3020
99 #define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
100 #define MTK_DP_ENC0_P0_3024 0x3024
101 #define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
102 #define MTK_DP_ENC0_P0_3028 0x3028
103 #define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
105 #define MTK_DP_ENC0_P0_302C 0x302c
106 #define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
108 #define MTK_DP_ENC0_P0_3030 0x3030
109 #define HTOTAL_SEL_DP_ENC0_P0 BIT(0)
121 #define MTK_DP_ENC0_P0_3034 0x3034
122 #define MTK_DP_ENC0_P0_3038 0x3038
124 #define MTK_DP_ENC0_P0_303C 0x303c
125 #define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0)
127 #define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)
133 #define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << 12)
137 #define MTK_DP_ENC0_P0_3040 0x3040
138 #define SDP_DOWN_CNT_DP_ENC0_P0_VAL 0x20
139 #define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0)
140 #define MTK_DP_ENC0_P0_304C 0x304c
143 #define MTK_DP_ENC0_P0_3064 0x3064
144 #define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
145 #define MTK_DP_ENC0_P0_3088 0x3088
151 #define MTK_DP_ENC0_P0_308C 0x308c
152 #define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
153 #define MTK_DP_ENC0_P0_3090 0x3090
154 #define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
155 #define MTK_DP_ENC0_P0_3094 0x3094
156 #define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)
157 #define MTK_DP_ENC0_P0_30A4 0x30a4
158 #define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)
159 #define MTK_DP_ENC0_P0_30A8 0x30a8
160 #define MTK_DP_ENC0_P0_30BC 0x30bc
161 #define ISRC_CONT_DP_ENC0_P0 BIT(0)
175 #define MTK_DP_ENC0_P0_30D8 0x30d8
176 #define MTK_DP_ENC0_P0_312C 0x312c
177 #define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
179 #define MTK_DP_ENC0_P0_3154 0x3154
180 #define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)
181 #define MTK_DP_ENC0_P0_3158 0x3158
182 #define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0)
183 #define MTK_DP_ENC0_P0_315C 0x315c
184 #define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
185 #define MTK_DP_ENC0_P0_3160 0x3160
186 #define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0)
187 #define MTK_DP_ENC0_P0_3164 0x3164
188 #define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
189 #define MTK_DP_ENC0_P0_3168 0x3168
190 #define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0)
191 #define MTK_DP_ENC0_P0_316C 0x316c
192 #define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0)
193 #define MTK_DP_ENC0_P0_3170 0x3170
194 #define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
195 #define MTK_DP_ENC0_P0_3174 0x3174
196 #define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0)
197 #define MTK_DP_ENC0_P0_3178 0x3178
198 #define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
199 #define MTK_DP_ENC0_P0_31B0 0x31b0
202 #define MTK_DP_ENC0_P0_31EC 0x31ec
206 /* offset: ENC1_OFFSET (0x3200) */
207 #define MTK_DP_ENC1_P0_3200 0x3200
208 #define MTK_DP_ENC1_P0_3280 0x3280
209 #define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)
212 #define MTK_DP_ENC1_P0_3300 0x3300
215 #define MTK_DP_ENC1_P0_3304 0x3304
219 #define MTK_DP_ENC1_P0_3324 0x3324
221 #define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX 0
222 #define MTK_DP_ENC1_P0_3364 0x3364
223 #define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL 0x20
224 #define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0)
227 #define MTK_DP_ENC1_P0_3368 0x3368
228 #define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0)
239 #define MTK_DP_ENC1_P0_3374 0x3374
241 #define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)
243 #define MTK_DP_ENC1_P0_33F4 0x33f4
244 #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
247 /* offset: TRANS_OFFSET (0x3400) */
248 #define MTK_DP_TRANS_P0_3400 0x3400
253 #define MTK_DP_TRANS_P0_3404 0x3404
254 #define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0)
255 #define MTK_DP_TRANS_P0_340C 0x340c
257 #define MTK_DP_TRANS_P0_3410 0x3410
258 #define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0)
264 #define MTK_DP_TRANS_P0_3414 0x3414
266 #define MTK_DP_TRANS_P0_3418 0x3418
267 #define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0)
273 #define MTK_DP_TRANS_P0_342C 0x342c
274 #define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6))
275 #define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0)
276 #define MTK_DP_TRANS_P0_3430 0x3430
277 #define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)
279 #define MTK_DP_TRANS_P0_34A4 0x34a4
281 #define MTK_DP_TRANS_P0_3540 0x3540
282 #define FEC_EN_DP_TRANS_P0_MASK BIT(0)
284 #define MTK_DP_TRANS_P0_3580 0x3580
289 #define MTK_DP_TRANS_P0_35C8 0x35c8
290 #define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
291 #define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
292 #define MTK_DP_TRANS_P0_35D0 0x35d0
293 #define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
294 #define MTK_DP_TRANS_P0_35F0 0x35f0
298 /* offset: AUX_OFFSET (0x3600) */
299 #define MTK_DP_AUX_P0_360C 0x360c
300 #define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)
301 #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
302 #define MTK_DP_AUX_P0_3614 0x3614
303 #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
305 #define MTK_DP_AUX_P0_3618 0x3618
307 #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
308 #define MTK_DP_AUX_P0_3620 0x3620
311 #define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0)
312 #define MTK_DP_AUX_P0_3624 0x3624
313 #define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
314 #define MTK_DP_AUX_P0_3628 0x3628
315 #define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0)
316 #define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0)
317 #define MTK_DP_AUX_P0_362C 0x362c
318 #define AUX_NO_LENGTH_AUX_TX_P0 BIT(0)
321 #define MTK_DP_AUX_P0_3630 0x3630
323 #define MTK_DP_AUX_P0_3634 0x3634
326 #define MTK_DP_AUX_P0_3640 0x3640
333 #define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0 BIT(0)
341 #define MTK_DP_AUX_P0_3644 0x3644
342 #define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
343 #define MTK_DP_AUX_P0_3648 0x3648
344 #define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
345 #define MTK_DP_AUX_P0_364C 0x364c
346 #define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)
347 #define MTK_DP_AUX_P0_3650 0x3650
351 #define MTK_DP_AUX_P0_3658 0x3658
352 #define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)
353 #define MTK_DP_AUX_P0_3690 0x3690
355 #define MTK_DP_AUX_P0_3704 0x3704
358 #define MTK_DP_AUX_P0_3708 0x3708
359 #define MTK_DP_AUX_P0_37C8 0x37c8
360 #define MTK_ATOP_EN_AUX_TX_P0 BIT(0)